Microchip | SY89872UMG

The SY89872UMG is a 2.5 V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create frequency-locked, lower speed version of the input Clock

Features:

• Guaranteed AC performance over temperature and voltage:
  • >2 GHz fMAX
  • <750ps tPD (matched delay between banks)
  • <15ps within-device skew
  • <200ps rise/fall time
• Low jitter design
  • <1psRMS cycle-to-cycle jitter
  • <10psPP total jitter
• Precision differential LVDS outputs
• Matched delay: all outputs have matched delay,independent of divider setting
• TTL/CMOS inputs for select and reset/disable
• Two output banks (matched delay)
  • Bank A: Buffered copy of input clock (undivided)
  • Bank B: Divided output (÷2, ÷4, ÷8, ÷16),two copies
• 2.5 V power supply
• Wide operating temperature range: –40°C to +85°C

Applications:

• OC-3 to OC-192 SONET/SDH applications
• Transponders
• Oscillators
• SONET/SDH line cards