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Microchip dsPIC33CK512MP608 Family of 16-Bit Digital Signal Controllers

100 MHz Single-Core DSC

Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MHz dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs are also ideal for switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.

These devices are also ideal for advanced sensing and control, touch, high-performance general-purpose and robust applications.

The dsPIC33CK product family by Microchip has many hardware features that help simplify functional safety certifications for ASIL-B and SIL-2 focused automotive and industrial safety-critical applications. The family offers ISO 26262 and IEC 61508 Functional Safety packages containing FMEDA report, safety manual, diagnostic libraries and more.


Special Features

  • 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
  • Programmable Pin Select (PPS) for peripheral pin function mapping
  • Parallel Master Port (PMP) for external data expansion
  • On-chip temperature sensor with direct ADC Module connection
  • Clock and Power Management
  • On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
  • Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
  • Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
  • Low-Power management modes - Sleep, Idle and Doze
  • Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)

Functional Safety Features

  • Dead-Man Timer (DMT) safety feature clocked by instruction fetches
  • Watch Dog Timer (WDT)
  • CodeGuard™ security for program FLASH
  • Programmable Cyclic Redundancy Check (CRC)
  • FLASH ECC Fault Injection testing feature
  • Flash OTP by ICSP™ write inhibit
  • Class B Safety Library, IEC 60730
  • RAM Memory Built-In Self Test (MBIST)
  • Two-Speed Start-up
  • Fail-Safe Clock Monitoring (FSCM)
  • Backup FRC (BFRC)
  • Capless Internal Voltage Regulator
  • Virtual Pins for Redundancy and Monitoring
  • Multiple redundant clock sources
  • I/O Port read-back
  • Analog peripherals redundancies
  • Hardware traps
  • SFR locks
  • Write protection
  • Shadow working registers