Microchip — PIC24FJ64GP205/GU205 16-Bit eXtreme Low-Power Microcontrollers

Microchip PIC24FJ64GP205/GU205 MCU Family

Featuring ultra-low-power operation (eXtreme Low Power)

The Microchip PIC24FJ64GP205/GU205 microcontroller (MCU) family addresses the evolving focus on secure protection features, low power operation and reliability with up to 64KB of ECC Flash, 8KB of RAM, along with several core independent peripherals (CIPs) and Full Speed USB 2.0 Host/Device/OTG. With sleep current down to a few hundreds of nA while retaining the complete RAM content, the PIC24FJ64GP205/GU205 MCU family is perfect for extending your battery life in any portable applications.

Supported in the MPLAB^® Code Configurator (MCC) tool, the development time gets significantly reduced by allowing you to configure the devices and libraries with just a few clicks. These MCUs offer hardware safety features and secure protection schemes, simplifying design of smart, safe, secure and connected applications.

Microchip PIC24FJ64GP205/GU205 MCUs feature protection schemes such as Flash OTP by ICSP™ Write Inhibit which allows the entire Flash to be configured as One-Time-Programmable (OTP) memory and CodeGuard™ Flash Security which facilitates to segment the memory and implement access restrictions. These features, together with our CryptoAuthentication™ chips, enable you to implement security in your applications.

Offering an extended operating temperature of up to 125°C with AEC Q100 Grade 1 qualification, this microcontroller family is also well suited for Automotive and Industrial applications. A range of hardware safety features in this family help you develop robust designs operating in extreme conditions. With a high-level of analog integration, the PIC24FJ64GP205/GU205 MCU family simplifies sensor interfacing and analog measurement, while reducing the overall system BoM cost.

eXtreme Low Power

• Ultra-low-power operation with sleep current down to nA with full RAM retention
• A range of power-saving modes to reduce current consumption, while balancing performance: PMD bits, DOZE, Idle, Sleep and Retention Sleep modes
• A range of Core Independent Peripherals (CIPs) that operate in power saving modes, while off-loading the Central Processing Unit (CPU)

Secure Protection Features

• Flash ‘One Time Programming’ (OTP) by ICSP™ Write Inhibit that offers an ability to disable Flash erase/write/debug operations using external programmers/debuggers
• CodeGuard™ Flash protection to manage memory partitions and access restrictions
• 120-bit Unique Device ID, 256 bytes User OTP and the above protection schemes make an ideal combination of complementary features to implement security together with the CryptoAuthentication™ devices in a secure application

Hardware Safety Features

• Flash with Error Correction Code (ECC) and Fault Injection for memory integrity check (Single error correction and Double error detection)
• Dead-Man Timer (DMT) clocked by instruction fetches for monitoring the health of software
• Windowed WatchDog Timer (WWDT) for system supervision
• CodeGuard™ Flash protection for memory partition and access restriction
• Fail-Safe Clock Monitor (FSCM) for clock fault management
• Enhanced Programmable Cyclic Redundancy Check (CRC), Programmable High-Low Voltage Detect (HLVD), Brown-out Reset (BOR) and Power-on Reset (POR)
• Class B Safety Library, IEC 60730