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AWS Announces RISC-V Support in the FreeRTOS Kernel


"RISC-V support is now available in the FreeRTOS kernel, a feature enabling embedded developers to create IoT applications on the officially supported FreeRTOS kernel for microcontrollers that use the free, open, and extensible RISC-V Instruction Set Architecture (ISA).

Now you have the flexibility to create applications that are portable across any FreeRTOS kernel-supported device and architecture." **

RISC-V support in the FreeRTOS kernel is available for any RISC-V microcontroller that uses the base ISA including Antmicro’s Renode emulator for the FUTUREM2GL-EVB Creative Board.

**As announced by Amazon on Feb 26, 2019

The Future-designed Creative Development Board, featuring Microchip’s IGLOO2 FPGA or SmartFusion2 SoC FPGA and Microchip’s LX series power devices. The Future - Microchip Creative Development Board boasts a 25k logic element (LE) FPGA, offering the lowest cost of entry for both software and hardware engineers who want to evaluate and implement their own unique designs.

Microchip’s IGLOO2 FPGAs and SmartFusion2 SoC FPGAs are ideal to implement a wide array of functions, including PCIe Gen2 control plane, image processing, motor control, I/O expansion and bridging. They also address fundamental requirements for advanced security, high reliability and low power in industrial, military, aviation, communications and medical applications.

Microchip has also introduced RISC-V, an open instruction set architecture, as a soft core to the IGLOO2 and SmartFusion2 FPGAs. In addition to FreeRTOS, which is supported by AWS, developers can run ThreadX and uC/OS on the RISC-V core.


Learn more about the Creative Development Board. Click here to request schematics, demonstration files and more.


Demo Projects using the Creative Board

Demos Description
Mi-V Tic Tac Toe Based on a Mi-V softcore processor design, play the classic Tic-Tac-Toe game by yourself or with a friend. This demo supports two touchscreen TFT from Adafruit (P1651 and P1947), and includes both a backlite control and a screensaver feature.
FreeRTOS Based on a Mi-V softcore processor design, this demo features a simple three task LED blinking program running in a FreeRTOS v8.2.3 environment. This design integrates a Terminal UART, LEDs, pushbuttons, a timer and a DDR2 controller to help you experience FreeRTOS in a FPGA setup.
ADC Read - Terminal (uses RISC-V) Based on a Mi-V softcore processor design, a reading from the ADC channel 0 or channel 2 will be echoed on a Terminal window on a host PC using the Avalanche’s user pushbuttons.
Out of the box - Risk-V Blinky (Hello World!) Out of the box demo. “Hello World!” text is sent through a Terminal connection at power-up or board reset. Terminal text is echoed afterward and board LEDs start blinking in a defined pattern. It provides a starting point to develop bare metal RISC-V applications.



  • Microchip IGLOO2 FPGA (M2GL025) or SmartFusion2 SoC FPGA (M2S025)
  • Microchip LX7167 DC/DC
  • 32M x 16 bit DDR2 SDRAM
  • Microchip 64Mbit serial flash SST26VF064B-104I/SM
  • Microchip 16/24-bit Delta-Sigma A/D Converter MCP3903-E/SS
  • On-board FTDI USB-JTAG adaptor
  • Arduino™ compatible expansion headers
  • MikroBUS™ compatible expansion headers
  • PMOD™ compatible expansion connector
  • Users buttons and LED


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