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A3P060-VQG100
ProASIC3 Series 60000 System Gate 71 I/O 1.575 V Surface Mount FPGA - VQFP-100
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| Herstellername: | Microchip | ||||||||||
| Standard Verpackungsart: | Product Variant Information section Verfügbare PaketePaketmenge:90 pro Tray | ||||||||||
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Microchip A3P060-VQG100 - Produktspezifikation
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*** Update for PCN 115312 ***Description of Change:Qualification of QMI519 as a new die attach material and CuPdAu as a new bond wire material for various products available in PLCC, QSOP, SOIC, SOIJ, SSOP, TSSOP, MQFP, TQFP, DFN, QFN, QFN-S, SQFN, TDFN, UDFN, UQFN, VDFN, VQFN, WQFN and TQFP packages assembled at MP3A, MTAI and MMT sites.Reason for Change:To improve manufacturability by qualifying QMI519 as a new die attach to standardize the use of PFAS free material and CuPdAu as a new bond wire material.Estimated First Ship Date:September 03, 2025 (date code: 2536)Revision History:July 22, 2025: Issued final notification.August 15, 2025: Re-issued the final notification to update the qualification report list, which now includes either a link to the qual report or an attached PDF file for each CCB. Updated the affected CPN list to removed EOL'ed CPNS: ATECC608A-MAHLG-T, ATECC608A-MAHVL-T, ATECC608A-MAHVM-T, ATECC508A-MAHPH-S, ATECC508A-MAHUW-T, ATECC608B MAH5O-T, ATECC508A-MAHKN-T, ATECC608B-MAHAF-S, ATECC508A-MAHKN-S, ATECC508A-MAH1A-T, ATECC608A-MAH4K-T, ATECC608A-MAH3P-T, ATECC608A MAH3Q-S, ATECC608A-MAH4W-T, ATECC608A-MAHAC-S, ATECC608A-MAHD3-S, ATECC608A-MAHGA-T, ATECC608A-MAHGX-T, ATECC508A-MAH2E-T, ATECC608A MAH2B-T, ATECC608A-MAH2G-S, ATECC608A-MAHT2-B, ATECC508A-MAH1C-S, ATECC508A-MAH1Q-S, ATECC508A-MAH1Q-T, ATECC608A-MAH1G-S, ATECC608A MAH1G-T, ATECC608A-MAH1K-S, ATECC508A-MAHWW-S, ATECC508A-MAHWW-T, ATECC608B-MAHAK-S, ATECC608B-MAHPA-T, ATECC608B-MAHSB-T, ATECC608B MAHSC-T, ATECC608A-MAH2U-T, ATECC608A-MAH2V-S, ATECC608A-MAH2X-S, ATECC608A-MAH2Y-S, ATECC608A-MAH3J-T and ATECC608A-MAH1W-T.September 18, 2025: Re-issued the final notification to add PFAS Elimination and Die Attach Explanation file and updated the affected CPN list to remove ATMEGA8535L-8JU, AT89LP6440-20JU, X34070T-H/ST, LX34050QPW-TR, LX3302AQPW-TR-EASY, LX3302AQPW-TR-C01, LX34311T-H/ST, LX34070AT-H/ST, LX34070-H/ST, LX34050QPW, LX3302AQPW-EASY, LX34070T-H/STVAO, LX3302AQPW-TR, LX34050QPW-TR-VAO, LX3302AQPW-TR-GM, LX34311T-H/STVAO, LX34070AT-H/STVAO, LX34070-H/STVAO, LX3302AQPW and LX34050QPW-VAO.
*****FPCN114582 UPDATE/MATERIAL CHANGEQualification of QMI519 as a new die attach material and CuPdAu as a new bond wire material for various products available in PLCC, QSOP, SOIC, SOIJ, SSOP, TSSOP, MQFP, TQFP, DFN, QFN, QFN-S, SQFN, TDFN, UDFN, UQFN, VDFN, VQFN, WQFN and TQFP packages assembled at MP3A, MTAI and MMT sites.*Re-issued the final notification to update the qualification report list, which now includes either a link to the qual report or an attached PDF file for each CCB. Updated the affected CPN list to removed EOL'ed CPNS: ATECC608A-MAHLG-T, ATECC608A-MAHVL-T, ATECC608AMAHVM-T, ATECC508A-MAHPH-S, ATECC508A-MAHUW-T, ATECC608B-MAH5O-T, ATECC508AMAHKN-T, ATECC608B-MAHAF-S, ATECC508A-MAHKN-S, ATECC508A-MAH1A-T, ATECC608AMAH4K-T, ATECC608A-MAH3P-T, ATECC608A-MAH3Q-S, ATECC608A-MAH4W-T, ATECC608AMAHAC-S, ATECC608A-MAHD3-S, ATECC608A-MAHGA-T, ATECC608A-MAHGX-T, ATECC508AMAH2E-T, ATECC608A-MAH2B-T, ATECC608A-MAH2G-S, ATECC608A-MAHT2-B, ATECC508AMAH1C-S, ATECC508A MAH1Q-S, ATECC508A-MAH1Q-T, ATECC608A-MAH1G-S, ATECC608AMAH1G-T, ATECC608A-MAH1K-S, ATECC508A-MAHWW-S, ATECC508A-MAHWW-T, ATECC608B-MAHAK-S, ATECC608B-MAHPA-T, ATECC608B-MAHSB-T, ATECC608B-MAHSC-T,ATECC608A MAH2U-T, ATECC608A-MAH2V-S, ATECC608A-MAH2X-S, ATECC608A-MAH2Y-S, ATECC608A-MAH3J-T and ATECC608A-MAH1W-T.
Description of Change:Qualification of QMI519 as a new die attach material and CuPdAu as a new bond wire material for various products available in PLCC, QSOP, SOIC, SOIJ, SSOP, TSSOP, MQFP, TQFP, DFN, QFN, QFN-S, SQFN, TDFN, UDFN, UQFN, VDFN, VQFN, WQFN and TQFP packages assembled at MP3A, MTAI and MMT sites.Reason for Change:To improve manufacturability by qualifying QMI519 as a new die attach to standardize the use of PFAS free material and CuPdAu as a new bond wire material.September 03, 2025 (date code: 2536)
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Microchip has released a new Datasheet for the ProASIC?3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. ? Corrected misaligned images?Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. ? Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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