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MPF050TL-FCVG484I
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Description of Change:Microchip has released a new Datasheet for the PolarFire? FPGA Datasheet of devices.Revision GReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 08 Apr 2026
Description of Change:? Added MPF050T and TC information throughout document.? Updated Table 1. Device Revisions.? Deprecated Feature: Use of External VERIFY_DIGEST with POR Digest Check for Fabric Components.Date Document Changes Effective: 05 Sep 2025
Description of Change:Implementation of Inner Box, Reel and MSL Bag Label changes for virtually ALL Microchip products.Reason for Change:To improve productivity by implementing inner box, reel and MSL bag label changes.
Description of Change:? Added reference to PolarFire Core products (MPFxxxTC) in Silicon and Libero Tool Status, Transceiver Switching Characteristics, Transceiver Protocol Characteristics, FPGA Programming Time, FPGA Bitstream Sizes, Digest Time, Verify Time, and Authentication Time. ? Changed silicon status of MPF050 to "Production ? all temperature grades" in Table 3-1. ? Added MPF500T offering in Table 3-4 Automotive T2. ? Updated note 7 under Recommended Operating Conditions for "XCVR calibration time". ? Added clarifying note 8 under Recommended Operating Conditions. ? Removed reference to PolarFire I/O Timing spreadsheet in User I/O Switching Characteristics. ? Corrected note under Transmitter Performance from "Untill specified" to "Unless specified". ? Updated notes under Power-On (Cold) Reset Initialization Sequence. ? Updated note under I/O Fast Recalibration Time (TRECALIB). ? SLVS18, SUBLVDS18 and SLVS25/33 Maximum input buffer speeds have been updated in Input Buffer Speed.Reason for Change: To improve productivity.
Description of Change:Released of updated Libero SoC v2022.3 for selected products in the PolarFire FPGA device family, including MPFxxx and RTPF device families as described in the attached customer notice details.Reason for Change:Release updated Libero SoC v2022.3 to prevent usage of device programming bitstreams that could result in false Power-On Reset digest check failures and tamper flag assertion, for scenarios where the user has enabled POR digest check settings for device components not included in the programming bitstream.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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