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  6. Asynchronous SRAM
  7. AS7C256A-15JIN

Alliance Memory | AS7C256A-15JIN

Manufacturer Part #

AS7C256A-15JIN

AS7C256A Series 256-kbit (32 K x 8) 5 V 15 ns CMOS Static RAM - SOJ-28

ECAD Model:
Mfr. Name: Alliance Memory
Standard Pkg:
Product Variant Information section
Date Code: 2401
Product Specification Section
Alliance Memory AS7C256A-15JIN - Technical Attributes
Attributes Table
Memory Density: 256kb
Memory Organization: 32 K x 8
Supply Voltage-Nom: 5V
Access Time-Max: 15ns
Temperature Grade: Industrial
Package Style:  SOJ-28
Mounting Method: Surface Mount
Features & Applications
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins.

The device enters standby mode when CE is high. CMOS standby mode consumes ≤11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages.

Pricing Section
Global Stock:
250
USA:
250
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
8 Weeks
Minimum Order:
1
Multiple Of:
1
Total
$2.08
USD
Quantity
Unit Price
1
$2.08
20
$2.04
40
$2.02
125
$1.98
250+
$1.94
Product Variant Information section