Manufacturer Part #
AS7C256A Series 256-kbit (32 K x 8) 5 V 15 ns CMOS Static RAM - SOJ-28
|Mfr. Name:||Alliance Memory|
|Standard Pkg:|| |
Product Variant Information section
25 per Tube
|Memory Organization:||32 K x 8|
|Mounting Method:||Surface Mount|
Features & Applications
The device enters standby mode when CE is high. CMOS standby mode consumes ≤11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.
The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages.
25 per Tube