Orders shipping outside of United States will be on hold while the company evaluates tariff impacts.Please contact your salesperson for assistance.
Free shipping within the continental US over $50. Conditions apply
Manufacturer Part #
AGL125V5-CSG196I
IGLOO
| | |||||||||||
| | |||||||||||
| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:348 per Tray | ||||||||||
| Date Code: | |||||||||||
Microchip AGL125V5-CSG196I - Product Specification
Shipping Information:
ECCN:
PCN Information:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=en&field2=AGL125V5-CSG196I&field4=Microchip&field18=https://p1na.futureelectronics.com/p/programmable-logic--fpga--fpga-flash/agl125v5-csg196i-microsemi-8105095
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=en&field2=AGL125V5-CSG196I&field4=Microchip&field18=https://p1na.futureelectronics.com/p/programmable-logic--fpga--fpga-flash/agl125v5-csg196i-microsemi-8105095
Available Packaging
Package Qty:
348 per Tray