
Manufacturer Part #
LAN91C111I-NU
LAN91C111I Series 3.3 V 10/100 Non-PCI Ethernet Single Chip MAC + PHY - TQFP-128
Microchip LAN91C111I-NU - Product Specification
Shipping Information:
ECCN:
PCN Information:
Revision History:December 22, 2021: Issued initial notification.June 02, 2023: Issued final notification. Updated the timetable summary. Provided estimated first ship date to be on June 25, 2023.Description of Change:Qualification of MMT as a new assembly site for selected SMSC LAN91C11xx device family available in 128L TQFP (14x14x1mm) package.Reason for Change:To improve on-time delivery performance by qualifying MMT as a new assembly site.
PCN Status:Initial NotificationPCN Type:Manufacturing ChangeDescription of Change:Qualification of MMT as a new assembly site for selected SMSC LAN91C11xx device family available in 128L TQFP (14x14x1mm) package.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve on-time delivery performance by qualifying MMT as a new assembly site.Change Implementation Status:In ProgressEstimated Qualification Completion Date:March 2022
Part Status:
Microchip LAN91C111I-NU - Technical Attributes
Data Rate: | 100Mbps |
Supply Voltage-Nom: | 3.3V |
Supply Current: | 100mA |
Duplex: | Half/Full Duplex |
Operating Temp Range: | -40°C to +85°C |
Storage Temperature Range: | -55°C to +150°C |
No of Functions / Channels: | 1 |
Interface Type: | MII |
No. of Transceivers: | 1 |
No of Terminals: | 128 |
Package Style: | TQFP-128 |
Mounting Method: | Surface Mount |
Features & Applications
The LAN91C111I-NU is a single chip Ethernet Controller designed for embedded applications, to implement the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps.
Features:
- Single Chip Ethernet Controller
- Dual Speed - 10/100 Mbps
- Fully Supports Full Duplex Switched Ethernet
- Supports Burst Data Transfer
- 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
- Enhanced Power Management Features
- Optional Configuration via Serial EEPROM Interface
- Supports 8, 16 and 32 Bit CPU Accesses
- Internal 32 Bit Wide Data Path (into Packet Buffer Memory)
- Built-in Transparent Arbitration for Slave Sequential Access Architecture
- Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues
- 3.3V Operation with 5V Tolerant I/O Buffers
- Single 25 MHz Reference Clock for Both PHY and MAC
- External 25 MHz Output Pin for an External PHY Supporting PHY's Physical Media
- Low Power CMOS Design
- Supports Multiple Embedded Processor Host Interfaces
- ARM
- SH
- Power PC
- Coldfire
- 680X0, 683XX
- MIPS R3000
- 3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate
- MII Management Serial Interface
- 128 Pin QFP lead-free RoHS compliant package
- 128 Pin TQFP 1.0 mm height lead-free RoHS compliant package
Available Packaging
Package Qty:
90 per Tray
Package Style:
TQFP-128
Mounting Method:
Surface Mount