Référence fabricant
MC100EP31DTG
MC100EP31 Series 3 GHz 5.5 V ECL D Flip-Flop with Set and Reset - TSSOP-8
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| Nom du fabricant: | onsemi | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :100 par Tube Style d'emballage :TSSOP-8 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
onsemi MC100EP31DTG - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Statut du produit:
onsemi MC100EP31DTG - Caractéristiques techniques
| Input Voltage-Max: | 2420mV |
| Temperature Range: | -40°C to +85°C |
| Supply Voltage-Nom: | 3V to 5.5V |
| Frequency-Max: | 3GHz |
| Style d'emballage : | TSSOP-8 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The MC100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The 100 Series contains temperature compensation.
Key Features:
- 340 ps Typical Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- Q Output Will Default LOW with Inputs Open or at VEE
- Pb-Free Packages are Available
Applications:
- Clock Distribution
Learn more about the MC100EP3x family of Timing Solutions
Emballages disponibles
Qté d'emballage(s) :
100 par Tube
Style d'emballage :
TSSOP-8
Méthode de montage :
Surface Mount