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Référence fabricant
ATSAMD20J18A-MU
SAMD20J Series 256 kB Flash 32 kB SRAM 48 MHz 32-Bit Microcontroller - QFN-64
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :260 par Tray Style d'emballage :QFN-64EP Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
Microchip ATSAMD20J18A-MU - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Description of Change:Updated the entire document to reflect new silicon revision H. Removed obsolete clarifications from Data Sheet ClarificationsAdded the following Errata:? Device: 1.5.22 One-Time Programmable Lock? SERCOM: 1.15.5 SERCOM I2C Client SDAHOLDReason for Change: To Improve Productivity
Microchip has released a new Datasheet for the SAM D20 Family Data Sheet of devices. Notification Status: FinalDescription of Change:SectionDescriptionPower Manager? Removed erroneous Clock Failure Detection content from the Overview? Removed erroneous Clock Failure Detection content from the Features? Updated Figure 15-2 in Selecting the Synchronous Clock Division Ratio? Removed erroneous Clock Failure Detection content from the Interrupts? Removed erroneous Clock Failure Detection content from the following registers:? CTRL? INTENCLR? INTENSET? INTFLAGSYSCTRL? Added a note to BOD33RDY in the PCLKSR Register? Removed erroneous Standby Sleep Mode from the ONDEMAND bitfield of the DFLLCTRL RegisterNVMCTRL? Added a new bullet of information to Procedure for Manual Page Writes (CTRLB.MANW=1)PORT - I/O? Updated the PINCFG Register Reset PropertyAC? Added a note to Offset CompensationSchematic Checklist? Removed an erroneous image from External Reset Circuit? Updated the MHz value in Table 36-5Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 03 Jan 2025
PCN Status:Final NotificationDescription of Change:Qualification of ATP7 as an additional assembly site for selected ATSAMC20xx, ATSAMC21xx, ATSAMD20xx, ATSAMD21xx and ATSAML21xx device families available in 64L VQFN (9x9x1mm) package.Reason for Change:To improve productivity and on-time delivery performance by qualifying ATP7 as an additional assembly site.
Description of Change:Qualification of MPHL as an additional final test site for selected ATSAMD20J14, ATSAMD20J15, ATSAMD20J16, ATSAMD20J17 and ATSAMD20J18 device families available in 64L VQFN (9x9x1mm) package.Reason for Change:To improve on-time delivery performance by qualifying MPHL as an additional final test site.Estimated First Ship Date:July 01, 2022 (date code: 2227)
Description of Change:Qualification of MPHL as an additional final test site for selected ATSAMD20J14, ATSAMD20J15, ATSAMD20J16, ATSAMD20J17 and ATSAMD20J18 device families available in 64L VQFN (9x9x1mm) package.Reason for Change:To improve on-time delivery performance by qualifying MPHL as an additional final test site.
Microchip has released a new Product Documents for the SAM D20 Datasheet of devices. If you are using one of these devices please read the document located at SAM D20 Datasheet.Notification Status: FinalDescription of Change:This revision includes numerous typographical corrections throughout the document. All other changes are described as follows:1) General: The SPI and I2C standards use the terminology "Master" and "Slave". The equivalent Microchip terminology, "Host" and "Client," is used in this document. This terminology has been updated throughout this document for this revision.2) RTC: Added a note to the RCONT bitfield in the READREQ Register.3) SERCOM SPI: Removed erroneous text in Host with Several Clients.4) TC: a) Updated the CTRLA Register with a new Register property for 8-bit, 16-bit and 32-bit Registers b) Updated the 8-bit COUNT Register with a new note and an updated Register Property c) Updated the 16-bit COUNT Register with a new note and an updated Register Property d) Updated the 32-bit COUNT Register with a new note and an updated Register Property5) Electrical Characteristics at 85C a) In SERCOM in SPI Mode Timing the table had minor formatting updates applied, and the typical and maximum values for tSCK switched b) In SERCOM in I2C Mode Timing minor formatting updates were applied to the table6) AEC-Q100 Electrical Characteristics at 125C: In SERCOM in SPI Mode Timing the table had minor formatting updates applied, and the typical and maximum values for tSCK switched.7) Acronyms and Abbreviations: Removed references to the TCC as this product does not contain a TCC.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 Mar 2022NOTE: Please be advised that this is a change to the document only the product has not been changed.
Statut du produit:
Microchip ATSAMD20J18A-MU - Caractéristiques techniques
| Family Name: | SAMD20 |
| Core Processor: | ARM Cortex M0+ |
| Program Memory Type: | Flash |
| Flash Size (Bytes): | 256kB |
| RAM Size: | 32kB |
| Speed: | 48MHz |
| No of I/O Lines: | 52 |
| InterfaceType / Connectivity: | I2C/SPI/UART/USART |
| Peripherals: | Brown-out Detect/POR/Reset/Watchdog |
| Supply Voltage: | 1.62V to 3.6V |
| Operating Temperature: | -40°C to +85°C |
| On-Chip ADC: | 20-chx12-bit |
| On-Chip DAC: | 1-chx10-bit |
| Watchdog Timers: | 1 |
| Style d'emballage : | QFN-64EP |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
Emballages disponibles
Qté d'emballage(s) :
260 par Tray
Style d'emballage :
QFN-64EP
Méthode de montage :
Surface Mount
