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Manufacturer Part #
A3P030-1QNG48
FPGA 48 VQFN 6x6x1mm TRAY
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:429 per Tray | ||||||||||
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Microchip A3P030-1QNG48 - Product Specification
Shipping Information:
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PCN Information:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Revision History:July 21, 2022: Issued initial notification.June 14, 2023: Issued final notification. Updated the wire material to CuPdAu/2N and die attach material to QMI519 in post change table. Updated table time summary. Revised the affected parts list. Provided estimated first ship date to be on June 15, 2023.August 25, 2023: Re-issued final notification to attach the Qual Report.Description of Change:Qualification of MTAI as a new assembly site for selected A3P0xx, A3PN0xx, AGL0xxxx and AGLN0xxxx device families available in 68L VQFN (8x8x1mm) and 48L VQFN (6x6x1mm)packages.Reason for Change:To improve manufacturability by qualifying MTAI as a new assembly site.
Revision History:June 30, 2023: Issued initial notification.July 12, 2023: Issued final notification. Attached the Qualification Report. Provided estimated first ship date to be on July 31, 2023. Revised CPN list, removed configurable parts.July 13, 2023: Re-issued final notification. Updated CPN list to add 48L VQFN.Description of Change:Qualification of MTAI as a new assembly site for selected A3P0xx-QNGxx, A3P030-xQNGxx, A3PN0xx-QNGxx, A3PN0xx-xQNGxx, AGL0xxVx-QNGxx and AGLN0xxVx-QNxx device families available in 48L VQFN (6x6x1mm) and 68L VQFN (8x8x1mm) packages.Reason for Change:To improve manufacturability by qualifying MTAI as a new assembly site.
Change Of Assembly and Material.Description of Change:Qualification of MTAI as a new assembly site for selected A3P0xx-QNGxx, A3P030-xQNGxx, A3PN0xx-QNGxx, A3PN0xx-xQNGxx, AGL0xxVx-QNGxx and AGLN0xxVx-QNxx device families available in 48L VQFN (6x6x1mm) and 68L VQFN (8x8x1mm) packages.Reason for Change:To improve manufacturability by qualifying MTAI as a new assembly site.
Revision History:July 21, 2022: Issued initial notification.June 13, 2023: Issued final notification. Updated the wire material to CuPdAu/2N and die attach material toQMI519 in post change table. Updated table time summary. Revised the affected parts list. Provided estimated first ship date to be on June 15, 2023.Description of Change:Qualification of MTAI as a new assembly site for selected A3P0xx, A3PN0xx, AGL0xxxx and AGLN0xxxx device families available in 68L VQFN (8x8x1mm) and 48L VQFN (6x6x1mm) packages.Reason for Change:To improve manufacturability by qualifying MTAI as a new assembly site.
Microchip has released a new Datasheet for the ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. • Corrected misaligned images—Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. • Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=en&field2=A3P030-1QNG48&field4=Microchip&field18=https://p1na.futureelectronics.com/p/semiconductors--programmable-logic--fpga-flash/a3p030-1qng48-microchip-1161817
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=en&field2=A3P030-1QNG48&field4=Microchip&field18=https://p1na.futureelectronics.com/p/semiconductors--programmable-logic--fpga-flash/a3p030-1qng48-microchip-1161817
Available Packaging
Package Qty:
429 per Tray