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Manufacturer Part #
AX2000-2FG896I
FPGA - Field Programmable Gate Array Axcelerator (AX)
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:27 per Tray | ||||||||||
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Microchip AX2000-2FG896I - Product Specification
Shipping Information:
ECCN:
PCN Information:
Microchip has released a new Datasheet for the Axcelerator Family FPGAs Datasheet of devices.Notification Status: FinalDescription of Change:The following is the list of changes in revision A of the document:• Migrated this document into Microchip template and updated the Microsemi links with Microchip links.• Updated document number to DS50003755A from 5172160.• Device AX125 has been discontinued in Table 1, Table 2, Table 3, and Table 4.• Package FG676 and CQ352 has been discontinued for device AX500 Table 1, Table 2, and Table 4.• Package FG896 and CG624 has been discontinued for device AX1000 Table 1, Table 2, and Table 4.• Package FG1152 has been discontinued for device AX2000 Table 1, Table 2, and Table 4.• In Table 2-2, under Parameter Range, Ambient temperature is changed to Junction temperature.• In Package Pin Assignments, for AX2000 device in CG624 package pin, E8 function has been updated from GND to GND/LP.Impacts to Data Sheet: See above details.Reason for Change: To Improve Productivity.Change Implementation Status: CompleteDate Document Changes Effective:October 10, 2024: Issued datasheet.October 16, 2024: Re-issued datasheet to update affected parts list.
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
Available Packaging
Package Qty:
27 per Tray