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Référence fabricant
MC100EP142FAG
MC100EP142 Series 3.3 V / 5 V 2.8 GHz ECL 9−Bit Shift Register - LQFP-32
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| Nom du fabricant: | onsemi | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :250 par Tray Style d'emballage :LQFP-32 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
onsemi MC100EP142FAG - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Initial Notification of ASE-SH Qualification for 32,48 and 100 lead LQFP.This is an Initial Product Change Notice to make customers aware that ASE-SH, located in Shanghai, China is being qualified as a supplemental assembly source for ON Semiconductor's 32, 48 and 100pin LQFP packages. The devices listed on this IPCN have historically been assembled at the Unisem located in Batam, Indonesia.
Statut du produit:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=MC100EP142FAG&field4=onsemi&field18=https://p1na.futureelectronics.com/de/p/semiconductors--logic--timing-solutions--high-bandwidth/mc100ep142fag-onsemi-1728021
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=MC100EP142FAG&field4=onsemi&field18=https://p1na.futureelectronics.com/de/p/semiconductors--logic--timing-solutions--high-bandwidth/mc100ep142fag-onsemi-1728021
onsemi MC100EP142FAG - Caractéristiques techniques
| Input Voltage-Max: | 2415mV |
| Temperature Range: | -40°C to +85°C |
| Supply Voltage-Nom: | 3V to 5.5V |
| Frequency-Max: | 2.8GHz |
| Style d'emballage : | LQFP-32 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The MC100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The MC100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from Bit 0 to Bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero, overriding CLK0 and CLK1 inputs. The 100 Series contains temperature compensation.
Key Features:
- Shift Frequency >2.8 GHz (Typical)
- 9-Bit for Byte-Parity Applications
- Asynchronous Master Reset
- Dual Clocks
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- Pb-Free Packages are Available
Applications:
- Byte Parity
Learn more about the MC100EP14x Family of Timing Solutions
Emballages disponibles
Qté d'emballage(s) :
250 par Tray
Style d'emballage :
LQFP-32
Méthode de montage :
Surface Mount