Référence fabricant
A42MX24-PQG208I
A42MX24 Series 912 LUTs 176 I/O 5.5 V Surface Mount FPGA - PQFP-208
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :24 par Tray | ||||||||||
| Code de date: | |||||||||||
Microchip A42MX24-PQG208I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Description of Change:Implement Microchip Part Aging Policy, Recertification and Combination rules, Labels and Packing Changes for selected Microsemi Field Programmable Gate Array (FPGA) and Mixed Signal and ASIC(MSA) products.Pre Change: Using Microsemi’s packing processPost Change:Using Microchip’s packing processPre and Post Change Summary:NOTE: See attached Packing Pre and Post Changes for the changes Impacts to Data Sheet:NoneChange Impact:NoneReason for Change:To improve productivity by standardizing the packing method as part of the integration of Microsemi and Microchip.Change Implementation Status:In ProgressEstimated Implementation Date: February 15, 2021 (date code: 2108)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and business conditions.Time Table Summary: see attachedRevision History:January 18, 2021: Issued final notification. Provided estimated first ship date to be on February 15, 2021.The change described in this PCN does not alter Microchip’s current regulatory compliance regarding the material content of the applicable products.
Description of Change: Implement Microchip Top marking changes for selected Microsemi Field-Programmable Gate Arrays (FPGAs) products available in various packages.Pre Change: Microsemi top marking format and traceability codePost Change: Microchip top marking format and traceability codePre and Post Change Summary: see attachedImpacts to Data Sheet: Where applicableChange Impact: NoneReason for Change:To improve manufacturability and traceability by standardizing marking format for selected Microsemi products as part of the integration of Microchip and Microsemi.Change Implementation Status: In ProgressEarliest Implementation Date: March 1, 2021 (Date code: 2110)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and businessconditions.Time Table Summary:
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
24 par Tray