Référence fabricant
M2GL005-1VFG400I
M2GL Series 703 kb RAM 171 I/O IGLOO2 FPGA - VFBGA-400
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :90 par Tray Style d'emballage :VFBGA-400 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | 2133 | ||||||||||
Microchip M2GL005-1VFG400I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the IGLOO� 2 FPGA and SmartFusion� 2 SoC FPGA Datasheet of devices.Description of Change: The following is a summary of the changes in revision B of this document.� Updated Table 3-7 by adding FCS158 related information (FD-292).� Updated the information against Access time with feed-through write timing in Table 3-229 to Table 3-233 (FD-276).
Microchip has released a new Datasheet for the AN4153 Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs of devices.Description of Change: The following is a summary of changes made in this revision: 1. Updated 1.1.2. Power Supply Sequencing. 2. Updated 1.2.2. I/O Glitch During Power-Down.Reason for Change: To Improve Productivity
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx FPGA device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In ProgressEstimated Implementation Date:December 16, 2021 (date code: 2151)
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In Progress
PCN Status: Final notificationPCN Type: Manufacturing ChangeDescription of Change:Release of an update to application note AN4153 (AC393) to include Smartfusion2/IGLOO2 FPGA VDD surge current when exiting system controller suspend mode case for selected products in FPGA family, including M2Sx and M2GLx devices..Impacts to Data Sheet: NoneChange Impact:NoneReason for Change:Release of the updated application note AN4153 section 1.3 �Limiting VDD surge current� which now includes the use case of Smartfusion2/IGLOO2 FPGA VDD surge current when exiting system controller suspend mode.Change Implementation Status:CompleteEstimated Implementation Date:June 23, 2021 (date code: 2126)
Description of Change:Implement Microchip Part Aging Policy, Recertification and Combination rules, Labels and Packing Changes for selected Microsemi Field Programmable Gate Array (FPGA) and Mixed Signal and ASIC(MSA) products.Pre Change: Using Microsemi�s packing processPost Change:Using Microchip�s packing processPre and Post Change Summary:NOTE: See attached Packing Pre and Post Changes for the changes Impacts to Data Sheet:NoneChange Impact:NoneReason for Change:To improve productivity by standardizing the packing method as part of the integration of Microsemi and Microchip.Change Implementation Status:In ProgressEstimated Implementation Date: February 15, 2021 (date code: 2108)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and business conditions.Time Table Summary: see attachedRevision History:January 18, 2021: Issued final notification. Provided estimated first ship date to be on February 15, 2021.The change described in this PCN does not alter Microchip�s current regulatory compliance regarding the material content of the applicable products.
Description of Change: Implement Microchip Top marking changes for selected Microsemi Field-Programmable Gate Arrays (FPGAs) products available in various packages.Pre Change: Microsemi top marking format and traceability codePost Change: Microchip top marking format and traceability codePre and Post Change Summary: see attachedImpacts to Data Sheet: Where applicableChange Impact: NoneReason for Change:To improve manufacturability and traceability by standardizing marking format for selected Microsemi products as part of the integration of Microchip and Microsemi.Change Implementation Status: In ProgressEarliest Implementation Date: March 1, 2021 (Date code: 2110)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and businessconditions.Time Table Summary:
Ongoing Software Quality Testing on Libero SoC Has Found a Static Timing Analysis (STA) Coverage Issue for Specific Scenarios for SmartFusion2, IGLOO2, RTG4, and PolarFire Product Families.Description:With Libero SoC v12.5, Libero SoC v12.5 SP1, and Libero SoC v11.9 SP6, netlist tie-off information is now correctly being passed to SmartTime for a complete static timing analysis.Reason for Change:Post-Layout timing database information for combinational cells inputs with constant tie-offs ("1" or "0") was incorrectly passed to SmartTime, preventing complete analysis of the path through the combinational cell.
Statut du produit:
Microchip M2GL005-1VFG400I - Caractéristiques techniques
| No of I/O Lines: | 171 |
| Flash Size (Bits): | 1Mb |
| RAM Size (Bits): | 703kb |
| Supply Voltage: | 1.14V to 1.26V |
| Operating Temp Range: | -40°C to +100°C |
| Storage Temperature Range: | -65°C to +150°C |
| Interface Type: | I2C |
| Temperature Grade: | Industrial |
| Moisture Sensitivity Level: | 3 |
| Style d'emballage : | VFBGA-400 |
| Méthode de montage : | Surface Mount |
Emballages disponibles
Qté d'emballage(s) :
90 par Tray
Style d'emballage :
VFBGA-400
Méthode de montage :
Surface Mount