Name: Nexperia 74AUP1G86GW,125
Brand: Nexperia
SKU: 2621597
Price: 0.0547 USD
Availability: InStock

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refer to technical specifications

Manufacturer Part #

74AUP1G86GW,125

74AUP Series 2 V SMT Single Low-Power 2-Input Exclusive-OR Gate - TSSOP-5

74AUP1G86GW,125 Datasheet 74AUP1G86GW,125 Documentation CMOS Logic General-purpose Logic Solutions
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Mfr. Name:	Nexperia
Standard Pkg:	Product Variant Information section Available Packaging Package Qty: 3000 per Reel Package Style: TSSOP-5 Mounting Method: Surface Mount
Date Code:

Nexperia 74AUP1G86GW,125 - Technical Attributes

Logic Circuit:	Exclusive OR GATE
No of Functions / Channels:	1
Supply Voltage-Nom:	0.8V to 3.6V
Power Dissipation:	250mW
Propagation Delay:	4.4ns
Operating Temperature:	-40°C to +125°C
Capacitance:	0.8pF
No of Inputs:	2
No of Outputs:	Single
High Level Output Current:	-4mA
Low Level Output Current:	4mA
No of Pins:	5
Quiescent Current:	0.5µA
Moisture Sensitivity Level:	1
Package Style:	TSSOP-5
Mounting Method:	Surface Mount

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Features & Applications

NXP is deeply committed to the logic market and continually invests in new process and package technologies, and packaging facilities, to ensure that the portfolio remains leading edge. They offer a very broad variety of innovative products, ranging from state-of-the-art solutions for emerging applications to specialty functions and proven, mature solutions that enhance virtually any application.The first CMOS (Complementary Metal–Oxide–Semiconductor) logic family of integrated circuits was introduced 1968. Initially CMOS logic was slower than LS-TTL; however, because the logic thresholds of CMOS were proportional to the power supply voltage, CMOS devices were well-adapted to battery-operated systems with simple power supplies.

Because of the incompatibility of the CD4000 series of chips with the previous TTL family, a new standard emerged which combined the best of the TTL family with the advantages of the CD4000 family. It was known as the 74HC (High performance silicon gate) family of devices.

With HC/HCT logic and LS-TTL logic competing in the market it became clear that a logic device that combined high speed, with low power dissipation and compatibility with older logic families was needed. A whole range of newer families has emerged that use CMOS technology. Some of the more important family designators of these newer devices includes LV/LVT/ALVT.

NXP supports a wide range of speed and performance options, with a focus on reduced power consumption and smaller size. The advanced CMOS processes deliver robust performance and have driven the expansion of the low-power 1.8- and 3.3-V logic families. All logic families are characterized and specified from -40 to +125 °C.

The 74AUP1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function.

The 74AUP1G86GW,125 is a 5V Low Power 2-input Exclusive OR Gate in TSSOP5.