AS7C256A-15JCNTR in Reel by Alliance Memory | Asynchrone | Future Electronics
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Alliance Memory | AS7C256A-15JCNTR

Référence fabricant

AS7C256A-15JCNTR

AS7C256A Series 256 kbit (32 K x 8) 5 V 15 ns CMOS Static RAM - SOJ-28

Modèle ECAD:
Nom du fabricant: Alliance Memory
Emballage standard:
Product Variant Information section
Code de date:
Product Specification Section
Alliance Memory AS7C256A-15JCNTR - Caractéristiques techniques
Attributes Table
Memory Density: 256kb
Memory Organization: 32 K x 8
Supply Voltage-Nom: 4.5V to 5.5V
Access Time-Max: 15ns
Temperature Grade: Commercial
Style d'emballage :  SOJ-28
Méthode de montage : Surface Mount
Fonctionnalités et applications
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins.

The device enters standby mode when CE is high. CMOS standby mode consumes =11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages.

A 256kb 5.0V Fast Asynchronous Alliance product that has a 32K x8 configuration, with commercial temperature range (0 to 70), and a 28-pin SOJ package. The part supports 15 nanoseconds speeds and is RoHS compliant. This particular part comes in tape and reel packaging.
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Pricing Section
Stock global :
0
États-Unis:
0
Sur commande :
0
Stock d'usine :Stock d'usine :
0
Délai d'usine :
8 Semaines
Commande minimale :
1000
Multiples de :
1000
Total 
1 840,00 $
USD
Quantité
Prix unitaire
1 000
$1.84
2 000+
$1.82
Product Variant Information section