Nexperia | 74HC377PW,118

The 74HC377PW,118 is a high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

Features:

• Ideal for addressable register applications
• Data enable for address and data synchronization applications
• Eight positive-edge triggered D-type flip-flops
• See “273” for master reset version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability: standard
• ICC category: MSI