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Manufacturer Part #
74HC273PW,118
74HC Series 6V Octal D-Type Flip-Flop w/ Reset Positive-Edge Trigger-TSSOP-20
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| Mfr. Name: | Nexperia | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:2500 per Reel Package Style:TSSOP-20 Mounting Method:Surface Mount | ||||||||||
| Date Code: | |||||||||||
Nexperia 74HC273PW,118 - Product Specification
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Nexperia 74HC273PW,118 - Technical Attributes
| Logic Circuit: | D-Type, Flip Flop IC |
| Family: | A/HC/T/U |
| No of Functions / Channels: | 8 |
| Supply Voltage-Nom: | 5V |
| Supply Current: | 8µA |
| Power Dissipation: | 500mW |
| Propagation Delay: | 150ns |
| Operating Temperature: | -40°C to +125°C |
| Capacitance: | 3.5pF |
| No of Inputs: | 8 |
| No of Outputs: | Eight |
| High Level Output Current: | -5.2mA |
| Low Level Output Current: | 5.2mA |
| No of Pins: | 20 |
| Moisture Sensitivity Level: | 1 |
| Package Style: | TSSOP-20 |
| Mounting Method: | Surface Mount |
Features & Applications
The 74HC273PW is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
Features:
- Ideal buffer for MOS microprocessor or memory
- Common clock and master reset
- Eight positive edge-triggered D-type flip-flops
- Complies with JEDEC standard no. 7A
- ESD protection:
- HBM EIA/JESD22-A114-C exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Specified from -40 Cel to +85Cel and from -40 Cel to +125 Cel
Available Packaging
Package Qty:
2500 per Reel
Package Style:
TSSOP-20
Mounting Method:
Surface Mount
