Microchip | 24LC64-I/ST

The 24LC64 is a 64 Kbit electrically Erasable PROM is organized as a single block of 8 K x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 2.5 V, with standby and active currents of only 1 μA and 1 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition.

The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space. The 24LC64 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP, DFN, TDFN and MSOP packages. The 24LC64 is also available in the 5-lead SOT-23 package.

Features:

• Single-Supply with Operation down to 2.5 V
• Low-Power CMOS Technology
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to 8 Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms, typical
• Self-timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-protect
• ESD Protection > 4,000 V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available