text.skipToContent text.skipToNavigation

Truck-Icon.svg Free shipping within the continental US over $50. Conditions apply

  1. home
  2. Semiconductors
  3. Memory ICs
  4. RAM (Random Access Memory)
  5. Static RAM
  6. Asynchronous SRAM
  7. AS7C34096A-12TIN

Alliance Memory | AS7C34096A-12TIN

Manufacturer Part #

AS7C34096A-12TIN

AS7C34096A Series 4 Mbit (512 K x 8) 3.3 V 12 ns CMOS Static RAM - TSOP 11-44

ECAD Model:
Mfr. Name: Alliance Memory
Standard Pkg:
Product Variant Information section
Date Code: 2401
Product Specification Section
Alliance Memory AS7C34096A-12TIN - Technical Attributes
Attributes Table
Memory Density: 4Mb
Memory Organization: 512 K x 8
Supply Voltage-Nom: 3.3V
Access Time-Max: 12ns
Temperature Grade: Industrial
Package Style:  TSOP II-44
Mounting Method: Surface Mount
Features & Applications
The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns areideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memorysystems. When CE is high the device enters standby mode.

The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chipdrives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

A 4MB 3.3V Fast Asynchronous Alliance product that has a 512K x8 configuration, with commercial temperature range (-40°C to 85°C), and a 44-pin TSOP II package. The part supports 12 nanoseconds speeds and is RoHS compliant.
Pricing Section
Global Stock:
34
USA:
34
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
8 Weeks
Minimum Order:
4
Multiple Of:
1
tariff icon
Tariff charges may apply if shipping to the United States. An estimate of tariff charges will be calculated at checkout.
Total
$22.88
USD
Quantity
Unit Price
4
$5.72
15
$5.65
25
$5.62
50
$5.59
100+
$5.51
Product Variant Information section