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Manufacturer Part #
ATTINY816-MFR
ATtiny Series 8 KB Flash 512 B SRAM 20 MHz 8-Bit Microcontroller - QFN-20
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:6000 per Reel | ||||||||||
| Date Code: | 2432 | ||||||||||
Microchip ATTINY816-MFR - Product Specification
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Description of Change:Qualification of MP3A as an additional assembly site for selected ATTINY406, ATTINY416, ATTINY426, ATTINY806, ATTINY816, ATTINY826, ATTINY1606, ATTINY1616, ATTINY1626, ATTINY3226, and AVR16EB20 device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change:To improve on-time delivery performance by qualifying MP3A as an additional assembly site.
PCN Status:Final NotificationDescription of Change:Qualification of MP3A as an additional assembly site for selected ATTINY16xx, ATTINY32xx, ATTINY4xx, AVR16EB20, MTCH1060xx, PIC16F1524xx, and ATTINY8xx device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change:To improve on-time delivery performance by qualifying MP3A as an additional assembly site.Change Implementation Status:In ProgressEstimated First Ship Date:30 November 2024 (date code: 2448)
PCN Status:Final NotificationDescription of Change:Qualification of MP3A as an additional assembly site for selected ATTINY406, ATTINY416, ATTINY426, ATTINY806, ATTINY816, ATTINY826, ATTINY1606, ATTINY1616, ATTINY1626, ATTINY3226, and AVR16EB20 device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change:To improve on-time delivery performance by qualifying MP3A as an additional assembly site.Change Implementation Status:In ProgressEstimated First Ship Date:July 5, 2024 (date code: 2427)
PCN Status:Initial NotificationDescription of Change:Qualification of MP3A as an additional assembly site for selected ATTINY16xx, ATTINY32xx, ATTINY4xx, AVR16EB20, MTCH1060xx, PIC16F1524xx, and ATTINY8xx device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change:To improve on-time delivery performance by qualifying MP3A as an additional assembly site.Change Implementation Status:In ProgressEstimated Qualification Completion Date:June 2024
***FPCN104919 Update ***Revision History:April 16, 2024: Issued final notification.May 08, 2024: Re-issued final notification. Updated pre and post change summary table to include package type and package width.Description of Change:Implement new carrier tape leader and trailer length for various packages shipped from MPHL site.Reason for Change:To improve manufacturability by standardizing the carrier tape and trailer length for various packages shipped from MPHL site.
Revision History:December 14, 2023: Issued initial notification.December 18, 2023: Re-issued to update Die Attach material and Lead-frame paddle size in the Qualification Plan.Description of Change:Qualification of MP3A as an additional assembly site for selected ATTINY406, ATTINY416, ATTINY426, ATTINY806, ATTINY816, ATTINY826, ATTINY1606, ATTINY1616, ATTINY1626, ATTINY3226, and AVR16EB20 device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change:To improve on-time delivery performance by qualifying MP3A as an additional assembly site.
Description of Change: Qualification of MP3A as an additional assembly site for selected ATTINY406, ATTINY416, ATTINY426, ATTINY806, ATTINY816, ATTINY826, ATTINY1606, ATTINY1616, ATTINY1626, ATTINY3226, and AVR16EB20 device families available in 20L VQFN (3x3x0.9mm) package.Reason for Change: To improve on-time delivery performance by qualifying MP3A as an additional assembly site.
Microchip has released a new Errata for the ATtiny417/814/816/817 Silicon Errata and Data Sheet Clarifications of devices. If you are using one of these devices please read the document located at ATtiny417/814/816/817 Silicon Errata and Data Sheet Clarifications.Notification Status: FinalDescription of Change: Revision Includes:• Document: – Editorial updates• Silicon Errata Issue added:– Device: 2.2.2. Write Operation Lost if Consecutive Writes to Specific Address Space– NVMCTRL: 2.6.1. Wrong Reset Value of NVMCTRL.CTRLA Register– TCD: 2.10.4. Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is Used• Silicon Errata Issues updated:– Device: 2.2.1. Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration Values– RTC: 2.7.1. Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler– TWI: 2.11.1. TIMEOUT Bit Field in the TWIn.MCTRLA Register is Corrupted• Silicon Errata Issue removed:– USART: Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode• Added new data sheet clarifications:– SLPCTRL: 3.1.1. Sleep Mode Activity Overview– ADC: 3.2.1. VREFA– Electrical Characteristics: 3.3.1. I/O Pin Characteristics, 3.3.2. Memory Programming SpecificationsImpacts to Data Sheet: None Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 03 Nov 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
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Available Packaging
Package Qty:
6000 per Reel