Manufacturer Part #
ARM Cortex-A5 Microprocessor IC SAMA5D2 1 Core, 32-Bit 500MHz 289-TFBGA (14x14)
|Standard Pkg:|| |
Product Variant Information section
119 per Tray
Microchip has released a new Product Documents for the SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications of devices.Description of Change: 1) Updated Table 1. SAMA5D2 SIP Silicon Device Identification.2) Updated 1. Silicon Issue Summary.3) Added in 4. Ethernet MAC (GMAC): - Screening registers not working4) Added in 7. Peripheral Touch Controller (PTC): - 7.1 Wrong pull-up value on PD[18:3] during reset5) Added in 12. ROM Code: - 12.3 Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit Reason for Change: To Improve Productivity Date Document Changes Effective: 25 Mar 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new Product Documents for the SAMA5D2 Family Silicon Errata and Data Sheet Clarification of devices.Description of Change:Added in 11. Peripheral Touch Controller (PTC):- 11.1 Wrong pull-up value on PD[18:3] during resetAdded in 16. ROM Code:- 16.7 Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit Reason for Change:To Improve Productivity
Description of Change:1) Global: In all Register Summary tables, bit order now shown from MSB to LSB.2) Pinout: Table Pin Description (all packages): modified direction of FLEXCOM3_IO3.3) Standard Boot Strategies: Supported External Crystal/External Clocks: updated clock frequency. NAND Flash PMECC Register: updated nbSectorPerPage description.4) Matrix (H64MX/H32MX): Register Summary: added MATRIX_SRTSR0 at offset 0x0280.5) Reset Controller (RSTC): RSTC_MR: updated reset value.6) Shutdown Controller (SHDWC): a)Updated Wake-Up Inputs. b) SHDW_SR: added note. c) SHDW_WUIR: added WKUPT1 detail.7) Real-time Clock (RTC): a) Replaced SLCK by slow clock throughout. b) Updated Reference Clock. c) Updated Alarm, RTC Internal Free-Running Counter Error Checking, Gregorian and Persian Modes, RTC Accurate Clock Calibration d) Updated Time/Calendar Update Timing Diagram, Gregorian and Persian Modes Update Sequence, UTC Time Update Timing Diagram, UTC Mode Update Sequence. e) RTC_CR: updated UPDCAL and UPDTIM bit descriptions. f) RTC_SCCR: updated description.8) Power Management Controller (PMC): a) Updated the table Clock Assignments with new rows for UART, TWI and SPI. b)PMC_PCKx: modified description of PRES field. 9) AHB Multiport DDR-SDRAM Controller (MPDDRC): a) Block Diagram: updated description. b) DDR2-SDRAM Initialization: added TRFC constraint content c) Corrected Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024/2048, Columns, 4 Banks d) MPDDRC_CR: updated NDQS bit description. e) MPDDRC_LPR: updated CHG_FRQ bit description.f) MPDDRC_TPR1: TRFC field name corrected from Row Cycle Delay to Row Refresh cycle.10) Static Memory Controller (SMC): In Description, replaced with one-bit error correction capability and supports two-bit error detection. In order to improve the overall system performance, the DATA phase of the transfer can be DMA-assisted. with new text.Scrambling/Unscrambling Function: replaced to prevent recovery with new text.11) DMA Controller (XDMAC): Updated: a) XDMAC Block Diagram. b) BXKBEN bit description in XDMAC_GCFG.12) LCD Controller (LCDC): a) Description: replaced AHB with system bus. b) Updated: LCDC PWM Controller, Power Management and Block Diagram c) Modified: 4:2:2 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3, 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3, 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x4, 0x5, 0x6, 0x7, Base Layer with Window Overlay Optimization d) Added figure in Pixel Clock Period Configuration.13) Ethernet MAC (GMAC): a) Changed all occurrences of GEMAC to GMAC. b) References to MDIO pin modified to GMDIO pin. c) Timestamp Unit: updated paragraph on GTSUCOMP and added figure GTSUCOMP Connection. d) GMAC_RRE.RXRER: modified description. e) GMAC_NSR: added note for the register reset value. f) GMAC_CBSCR: corrected inverted bits. g) GMAC_EFTSH: updated offset. h) Modified base offset and index for registers: GMAC_ISRPQx, GMAC_TBQBAPQx, GMAC_RBQBAPQx, GMAC_RBSRPQx, GMAC_IERPQx, GMAC_IDRPQx, GMAC_IMRPQx14) Audio Class D Amplifier (CLASSD): a) Description: added a note. b) Embedded Characteristics: modified first item in the list. c) CLASSD Block Diagram: added note. 15) Serial Synchronous Controller (SSC): SSC_TFMR: updated DATDEF bit description16) Two-wire Interface (TWIHS): a) Updated Master Performs a General Call. b) Updated TWIHS Read Operation with Multiple Data Bytes + Write Operation with Multiple Data Bytes (Sr). c) TWIHS_CWGR: updated CLDIV and CHDIV bit descriptions. d) Added detail: This register reads 0 if the FIFO is disabled (see TWI_CR to enable/disable the internal FIFO) in: TWIHS_FMR,TWIHS_FLR, TWIHS_FSR, TWIHS_FIMR17) Flexible Serial Communication Controller (FLEXCOM): a) Updated FLEXCOM Block Diagram. b) Updated Master Perf
Notification text:SYST-14SSVQ730Microchip has released a new Product Documents for the SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications of devices. If you are using one of these devices please read the attached document .Description of Change: 1 Added in 10. Real-Time Clock (RTC):- 10.1 RTC_SR.TDERR flag is stuck at 0- 10.2 Read access truncated to the first 24 bits for register RTC_TIMALR (UTC_MODE)2. Updated in 11. ROM Code:- 11.1 UART blocks USB connection to SAM-BA MonitorReason for Change: To Improve Productivity
Description of Change:1) Added 10.1 UART2 IOSET 2 selection blocks USB connection to SAM-BA Monitor. 2) Updated 15. Data Sheet Clarifications for SAMA5D2 Reason for Change: To Improve Productivity.Date Document Changes Effective: 30 Jan 2020NOTE: Please be advised that this is a change to the document only the product has not been changed.
Data Sheet - SAMA5D2 MPU SiP with up to 1Gbit DDR2 or 2Gbit LPDDR2Microchip has released a new Product Documents for the SAMA5D2 MPU SiP with up to 1Gbit DDR2 or 2Gbit LPDDR2 of devices.Notification Status: FinalDescription of Change: 1) Updated memory references in Reference Documents2) Updated burst, write, read latencies in LPDDR2-SDRAM Features3) Added 8.1 Recommended Thermal Operating Conditions in Electrical CharacteristicsImpacts to Data Sheet: NoneReason for Change: To Improve ManufacturabilityChange Implementation Status: CompleteDate Document Changes Effective: 28 Jan 2020NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new DeviceDoc for the SAMA5D2 Family Silicon Errata and Data Sheet Clarification of devices.Description of Change:1) Added 12.1 Fault Protection to Hi-Z for PWMx output not functional2) Added 15.3 Sampling clock tuning procedure3) Updated 21. Data Sheet Clarifications.Reason for Change: To Improve ProductivityDate Document Changes Effective: 20 Feb 2019NOTE: Please be advised that this is a change to the document only the product has not been changed.
|Core Processor:||ARM Cortex A5|
|Program Memory Type:||Flash|
|Data Bus Width:||32b|
|Mounting Method:||Surface Mount|
Features & Applications
The SAMA5D27 Wireless SOM1 (WLSOM1) is a small, single-sided System-on-Module (SoM) from Microchip which combines a high-performance microprocessor based on the Arm® Cortex®-A5 core with Wi-Fi® and Bluetooth® wireless connectivity.
• IoT devices
• Smart appliances
• Healthcare equipment
• Human-machine interfaces
• Access control panels
• Home automation
• Industrial automation
• 10/100 Ethernet PHY
• USB Device and Host interfaces
• Two CAN interfaces
• 64Mbit serial Quad I/O Flash memory
• 128kbytes of SRAM
• Cache memory:
• 32kbytes in L1, 128kbytes in L2
• Graphics controller
• 18-bit graphic LCD controller
• Camera interface
• 51-channel DMA controller
• Operating-temperature range: -40°C to 85°C
119 per Tray