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Manufacturer Part #
ATSAMA5D28C-D1G-CUR
System in Package (SiP) integrates the ARM® Cortex®-A5 processor-based
Microchip ATSAMA5D28C-D1G-CUR - Product Specification
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Microchip has released a new Errata for the SAMA5D2 SIP Family Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change: Updated 1. Silicon Issue Summary Added in 6. Controller Area Network (MCAN): - 6.13. Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes Added in 13. Secure Digital MultiMedia Card Controller (SDMMC): - 13.3. SDMMC I/O calibration does not workImpacts to Data Sheet: NoneChange Implementation Status: CompleteDate Document Changes Effective: 06 Sep 2022
Description of Change:Qualification of a new die size and mold compound for Die # 2 for selected catalog part numbers (CPN) ATSAMA5D28C-D1G-CU, ATSAMA5D27C-D1G-CU, ATSAMA5D28C-D1G-CUR, ATSAMA5D27C-D1G-CUR, ATSAMA5D27C-D5M-CU & ATSAMA5D27C-D5M-CUR available in 289L TFBGA (14x14x1.2mm) and U2 component for selected catalog part number (CPN) ATSAMA5D27-SOM1 available in 176L MODULE (40x38x6.34mm) packages.Reason for Change:To improve manufacturability by qualifying a new die size and new mold compound.
Microchip has released a new Product Documents for the SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications of devicesDescription of Change: 1) Updated 1. Silicon Issue Summary.2) Deleted in 6. Controller Area Network (MCAN):- Message order inversion when transmitting from dedicated Tx Buffers configured with same message ID Reason for Change: To Improve Productivity Date Document Changes Effective: 15 Mar 202
Microchip has released a new Product Documents for the SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications of devices.Notification Status: FinalDescription of Change: Updated 1. Silicon Issue Summary. Added in 6. Controller Area Network (MCAN): - 6.12 Debug message handling state machine not reset to Idle state when CCCR.INIT is set - 6.13 Message order inversion when transmitting from dedicated Tx Buffers configured with same message ID Added in 17. Watchdog Timer (WDT): - 17.1 Restart command of WDT may reset the DDR controllerImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 13 Sept 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new Product Documents for the SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications of devices.Description of Change: 1) Updated Table 1. SAMA5D2 SIP Silicon Device Identification.2) Updated 1. Silicon Issue Summary.3) Added in 4. Ethernet MAC (GMAC): - Screening registers not working4) Added in 7. Peripheral Touch Controller (PTC): - 7.1 Wrong pull-up value on PD[18:3] during reset5) Added in 12. ROM Code: - 12.3 Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit Reason for Change: To Improve Productivity Date Document Changes Effective: 25 Mar 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.
Part Status:
Available Packaging
Package Qty:
1000 per Std. Mfr. Pkg