Manufacturer Part #
MPF100T-FCSG325E
MPF Series 284 I/O Lines SMT PolarFire™ Non-Volatile FPGA - Flip Chip 325
| | |||||||||||
| | |||||||||||
| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:1 per Tray | ||||||||||
| Date Code: | |||||||||||
Microchip MPF100T-FCSG325E - Product Specification
Shipping Information:
ECCN:
PCN Information:
Description of Change:Released of updated Libero SoC v2022.3 for selected products in the PolarFire FPGA device family, including MPFxxx and RTPF device families as described in the attached customer notice details.Reason for Change:Release updated Libero SoC v2022.3 to prevent usage of device programming bitstreams that could result in false Power-On Reset digest check failures and tamper flag assertion, for scenarios where the user has enabled POR digest check settings for device components not included in the programming bitstream.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Description of Change:Release of revised timing data in Libero SoC v2021.2 for selected products in the PolarFire FPGA device family, including selected CPSOM-MPFxxx, MPF100Txxx, MPF200Txxx, MPF300Txxx and MPF500Txxx device families.Reason for Change:Release updated PolarFire FPGA timing data along with Libero SoC v2021.2 to improve the accuracy of Static Timing Analysis (STA) performed on PolarFire designs, as described in the attached Customer Notice.
Description of Change:Implement Microchip Part Aging Policy, Recertification and Combination rules, Labels and Packing Changes for selected Microsemi Field Programmable Gate Array (FPGA) and Mixed Signal and ASIC(MSA) products.Pre Change: Using Microsemi�s packing processPost Change:Using Microchip�s packing processPre and Post Change Summary:NOTE: See attached Packing Pre and Post Changes for the changes Impacts to Data Sheet:NoneChange Impact:NoneReason for Change:To improve productivity by standardizing the packing method as part of the integration of Microsemi and Microchip.Change Implementation Status:In ProgressEstimated Implementation Date: February 15, 2021 (date code: 2108)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and business conditions.Time Table Summary: see attachedRevision History:January 18, 2021: Issued final notification. Provided estimated first ship date to be on February 15, 2021.The change described in this PCN does not alter Microchip�s current regulatory compliance regarding the material content of the applicable products.
Description of Change: Implement Microchip Top marking changes for selected Microsemi Field-Programmable Gate Arrays (FPGAs) products available in various packages.Pre Change: Microsemi top marking format and traceability codePost Change: Microchip top marking format and traceability codePre and Post Change Summary: see attachedImpacts to Data Sheet: Where applicableChange Impact: NoneReason for Change:To improve manufacturability and traceability by standardizing marking format for selected Microsemi products as part of the integration of Microchip and Microsemi.Change Implementation Status: In ProgressEarliest Implementation Date: March 1, 2021 (Date code: 2110)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and businessconditions.Time Table Summary:
PolarFire FPGA VICM Clarification for HSIODescription:This is a PolarFire Datasheet documentation change to the note for table 16 which relaxes the HSIO differential receiver maximum input common mode from a maximum VICM value of VDDI � 0.4 V to a new maximum VICM value of VDDI 0.24 V.Reason for ChangeThis change is to correct the PolarFire Datasheet table 16 notes that were too restrictive for HSIO differential receiver input common modes maximum ranges.
Maximum Read Frequency on Certain LSRAM Read Modes Has Been Reduced.DescriptionThe following LSRAM configurations have derated FMAX specifications.Reason for ChangeOn-going QA testing and verification exposed a timing criticality in a critical path within the LSRAM.Application ImpactUsers should upgrade to Libero 12.6 and re-run static timing using SmartTime if they are using one of the above LSRAM configurations and the design is running faster than the new limits listed in the table above.Method of Identifying Changed ProductBy part number.
Part Status:
Available Packaging
Package Qty:
1 per Tray