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Manufacturer Part #
MPF500T-1FCG1152E
FPGA - Field Programmable Gate Array 33.73Mb 24 TransCh 250Mbps-12.7Gbps
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:1 per Tray | ||||||||||
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Microchip MPF500T-1FCG1152E - Product Specification
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PCN Information:
Description of Change:Release of revised timing data in Libero SoC v2021.2 for selected products in the PolarFire FPGAdevice family, including selected CPSOM-MPFxxx, MPF100Txxx, MPF200Txxx, MPF300Txxx and MPF500Txxx device families.Reason for Change:Release updated PolarFire FPGA timing data along with Libero SoC v2021.2 to improve the accuracy ofStatic Timing Analysis (STA) performed on PolarFire designs, as described in the attached Customer Notice.
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Implement firmware update and step marking changes for selected MPF050xx, MPF100xx, MPF200xx, MPF300xx, MPF500xx, MPFS02xx, MPFS09xx, MPFS16xx and MPFS25xx device families available in various packages. Refer to the PDF found in the Attachments section for data sheet change detail.Reason for Change:To improve productivity by updating the firmware for zeroization time and implement step marking changes for FPGA devices.
Microchip has released a new Datasheet for the PolarFire? FPGA Datasheet of devices.Notification Status: FinalDescription of Change:? Added the MPF050T part number status to production.? Added two notes to Table 4-3 to explain how weak pullup and weak pulldown resistors should be calculated.? Corrected Note 6 of Table 4-4. The maximum time allowed was listed as 300 ?s and should be 300 ns.? Added HSIO clock skew with bridging for MPF050T device in Table 5-17.? Added PLL output jitter specification for FOUT slower than 1.5 MHz in Table 5-18. Also clarified Note 5 and 6.? Added footnote to Table 5-106.? Updated the SPI Timing section for clarification. No changes to silicon have occurred. See 5.10.2. SPI Switching Characteristics.? Clarified Note 1 and condition in Table 5-106.? Changed ?CDR PPM tolerance? to ?CDR frequency tolerance? for better clarity in 5.4.5. Receiver Performance.? Updated VDDI3 power-up requirements in section 5.9. Power-Up to Functional Timing and 5.9.3.2. I/O-Related Supplies.? Updated 5.6.6. Zeroization Time and 5.8.7. User Voltage Detector Characteristics sections as per PCN.? Updated Table 5-37.? Updated 5.2.4. RC Oscillators.? Corrected item in Table 5-7. Fabric clock maximum frequency for LPDDR3 on -STD speed grade devices was listed as 133 MHz and should be 100 MHz.? Updated Table 5-107 to support the full military range.? Authentication Service IDs were swapped. Table 5-81 was updated.? Corrected Table 3 for military grade devices to lead and tin.? Redirected the Device Offering list to a separate document entitled PolarFire? FPGA Product Overview.Impacts to Data Sheet: See above details.Change Implementation Status: CompleteDate Document Changes Effective: 17 Apr 2024
Microchip has released a new Document for the PolarFire? FPGA Production Devices Errata of devices. If you are using one of these devices please read the document located at PolarFire? FPGA Production Devices Errata.Notification Status: FinalDescription of Change: Defeatured PCIe SECDED reporting. More information about this is available in the change impact analysis document.Added references to MPF050T in Errata Summary and Supported Transceiver Protocols.Updated to Microchip template.Updated document number from ER0218 to DS80001111.Impacts to Data Sheet: NoneChange Implementation Status: CompleteDate Document Changes Effective: 30 Jan 2024NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices::N/A
Description of Change:Release of updated Libero SoC v2023.2 for selected products in the PolarFire FPGA, PolarFire SoC and RT PolarFire FPGA device families, including MPFxxx and RTPF device families. Refer to the PDF found in the Attachments section for additional details. Reason for Change:The important updates in Libero SoC v2023.2 address issues in previous software versions that could result in either: High-Speed I/O Clock functional issues, device I/O performance outside the datasheet specifications, or registered I/O interface performance outside the user design's Static Timing Analysis results. Refer to the PDF attached to this PCN for additional details.
Description of Change:Released of updated Libero SoC v2022.3 and PF_CCC v2.2.220 for selected products in the PolarFire FPGA device family, including MPFxxx and RTPF device families.Reason for Change:Release updated Libero SoC v2022.3 and later to resolve issue that occurred on designs that were updated to Libero SoC v2022.2, where an existing PF_CCC core component instance was updated to v2.2.214, resulting in the PF_CCC core being re-generated with an incorrect PLL LOCK_CNT parameter value of 0x0. The latest version of Libero SoC is available for download on the webpage below:
Description of Change:Released of updated Libero SoC v2022.3 for selected products in the PolarFire FPGA device family, including MPFxxx and RTPF device families as described in the attached customer notice details.Reason for Change:Release updated Libero SoC v2022.3 to prevent usage of device programming bitstreams that could result in false Power-On Reset digest check failures and tamper flag assertion, for scenarios where the user has enabled POR digest check settings for device components not included in the programming bitstream.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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