Kingston — Embedded DRAM Components

Features (DDR3/3L)

• Double Data Rate (DDR) architecture: Two data transfers per clock cycle
• High-speed data transfer realized by 8-bit prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS alignment:
  • Edge-aligned with data for READS
  • Center-aligned with data for WRITES
• Differential clock inputs: CK and /CK
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Data Mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality:
  • Synchronous ODT
  • Dynamic ODT
  • Asynchronous ODT
• Multi-Purpose Register (MPR) for pre-defined pattern read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• RESET pin for power-up sequence and reset function
• SRT range: Normal/extended
• Programmable output driver impedance control

Features (DDR4)

• Double-data-rate architecture: Two data transfers per clock cycle
• High-speed data transfer realized by the 8-bit prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) transmitted/received with data for capturing data at the receiver
• DQS alignment:
  • Edge-aligned with data for READs
  • Center-aligned with data for WRITEs
• Differential clock inputs: CK_t and CK_c
• DLL aligns DQ and DQS transitions with CK transitions
• Data Mask (DM): Write data-in at both rising and falling edges of the data strobe
• Write Cycle Redundancy Code (CRC) is supported
• Programmable preamble for read and write operations
• Programmable burst length: 4/8 with both nibble sequential and interleave modes
• Burst Length (BL) switch on the fly
• Driver strength selected by MRS
• Dynamic On-Die Termination (ODT) is supported

• Two termination states:
  • RTT PARK
  • RTT NOM (switchable by ODT pin)
• Asynchronous RESET pin is supported
• ZQ calibration is supported
• Write Levelization is supported
• RoHS compliance
• Internal Vref DQ level generation is available
• TCAR (Temperature Controlled Auto Refresh) mode is supported
• LP ASR (Low Power Auto Self Refresh) mode is supported
• Command Address (CA) Parity mode is supported
• Per DRAM Addressability (PDA) is supported
• Fine granularity refresh is supported
• Geardown mode: 1/2 rate, 1/4 rate
• Self Refresh Abort is supported
• Maximum power saving mode is supported
• Banks Grouping applied:
  • CAS-to-CAS latency (tCCD_L, tCCD_S) available for the same or different bank group accesses
• DMI pin: Supports write data masking and DBI_dc functionality

Features (LPDDR4)

• Double-data-rate architecture: Two data transfers per clock cycle
• High-speed data transfer realized by 8-bit prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) transmitted/received with data for capturing data at the receiver
• DQS alignment:
  • Edge-aligned with data for READs
  • Center-aligned with data for WRITEs
• Differential clock inputs: CK_t and CK_c
• DLL aligns DQ and DQS transitions with CK transitions
• Data Mask (DM): Write data-in at both rising and falling edges of the data strobe
• Write Cycle Redundancy Code (CRC) is supported
• Programmable preamble for read and write is supported
• Programmable burst length: 4/8 with both nibble sequential and interleave modes
• BL switch on the fly
• Driver strength selected by MRS
• Dynamic On-Die Termination (ODT) is supported
• Two termination states:
  • RTT_PARK
  • RTT_NOM (switchable by ODT pin)
• Asynchronous RESET pin is supported
• Maximum power saving mode is supported
• Banks Grouping applied:
  • CAS-to-CAS latency (tCCD_L, tCCD_S) available for same or different bank group accesses
• ZQ calibration is supported

• Write Levelization is supported
• RoHS compliance
• Internal Vref DQ level generation is available
• TCAR (Temperature Controlled Auto Refresh) mode is supported
• LP ASR (Low Power Auto Self Refresh) mode is supported
• Command Address (CA) Parity mode is supported
• Per DRAM Addressability (PDA) is supported
• Fine granularity refresh is supported
• Geardown mode: 1/2 rate, 1/4 rate
• Self Refresh Abort is supported
• DMI pin: Supports write data masking and DBI_dc functionality
• Low power consumption
• Per Bank Refresh
• JEDEC LPDDR4 compliance: Fully compliant with the Low Power Double Data Rate 4 (LPDDR4) Specification
• Partial Array Self-Refresh (PASR):
  • Bank Masking
  • Segment Masking
• Auto Temperature Compensated Self-Refresh (ATCSR):
  • Built-in temperature sensor
  • All bank auto refresh and directed per bank auto refresh supported
• Commands entered on both rising and falling CK_t edge; data and data mask referenced to both edges of DQS_t
• DMI pin: Supports write data masking and DBI_dc functionality

Applications

• Industrial IoT/robotics
• Factory automation
• 5G networking/telecommunications communication modules
  • Wi-Fi routers
  • Mesh devices
• Wearables
  • Smart-watches
  • Health monitors
  • AR and VR

• Smart homes
  • Sound bars
  • Thermostats
  • Fitness equipment
  • Vacuums
  • Beds
  • Faucets
• Smart Cities
  • HVAC
  • Lighting
  • Power monitoring/metering
  • Parking meters