

Manufacturer Part #
A42MX24-PQG208I
A42MX24 Series 912 LUTs 176 I/O 5.5 V Surface Mount FPGA - PQFP-208
Microchip A42MX24-PQG208I - Product Specification
Shipping Information:
ECCN:
PCN Information:
EOL Description:The selected A42MX16, A42MX24 and A42MX36 device families will be moving to End of Life (EOL) status effective today. These selected device families will no longer be offered after December 1, 2026. Please review the attached parts affected list below for details about replacement parts if applicable.*Note 1:Aligning with our commitment to product longevity, Microchip is currently qualifying a new assembly site as a potential alternative manufacturing source for the affected products. If the qualification is successfully completed, we intend to cancel the EOL notice and resume standard supply through the newly qualified site. We strongly encourage you to place your LTB orders as soon as possible to ensure uninterrupted supply and to mitigate any potential supply gaps during the qualification period. Please note that all LTB orders will be processed as NCNR. If the new assembly site is successfully qualified, a PCN will be issued to inform you of the change to assembly location and the EOL notice will be cancelled, which will also prompt a cancellation notice. At that time, clients will have the option to extend deliveries of their LTB orders beyond the LTS date. Reason for EOL:No longer have manufacturing support for the CPN listed in the attachment.Estimated Effective Dates:Customers affected by this EOL notice are advised to place last time buy (LTB) orders as follows:Last date for bookings (LTB): December 1, 2025Last date for shipments (LTS): December 1, 2026
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
Available Packaging
Package Qty:
24 per Tray