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Manufacturer Part #

LPC1788FET180,551

LPC17xx Series 512 kB Flash 96 kB RAM SMT 32-Bit-Microcontroller - TFBGA-180

ECAD Model:
Mfr. Name: NXP
Standard Pkg:
Product Variant Information section
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Product Specification Section
NXP LPC1788FET180,551 - Technical Attributes
Attributes Table
Family Name: LPC17xx
Core Processor: ARM Cortex M3
Program Memory Type: Flash
Flash Size (Bytes): 512kB
RAM Size: 96kB
Speed: 100MHz
No of I/O Lines: 165
InterfaceType / Connectivity: Ethernet/I2C/I2S/LCD Graphic Controller/SPI/SSP/UART/USB
Peripherals: Ethernet/I2C/I2S/On-Chip-ADC/PWM/SPI/SSP/UART/USB/Watchdog
Number Of Timers: 4
Supply Voltage: 2.4V to 3.6V
Operating Temperature: -40°C to +85°C
On-Chip ADC: 8-chx12-bit
Watchdog Timers: 1
Package Style:  TFBGA-180
Mounting Method: Surface Mount
Features & Applications
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.

The Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches.

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x is targeted to operate at up to 100 MHz CPU frequency.

Features and Benefits:

  • Functional replacement for LPC23xx and 24xx family devices
  • System:
    • ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included
    • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
    • Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time
    • Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy
Pricing Section
Global Stock:
0
USA:
0
On Order:
0
Factory Stock:Factory Stock:
-1
Factory Lead Time:
16 Weeks
Minimum Order:
189
Multiple Of:
189
Total
$2,020.41
USD
Quantity
Unit Price
189+
$10.69
Product Variant Information section