Features and Applications
The MC100EP51DG is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.
The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave and thus the outputs, upon a positive transition of the clock.
- 350 ps Typical Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- These Devices are Pb−Free and are RoHS Compliant