Les commandes expédiées à l’extérieur des États-Unis seront en attente pendant que l’entreprise évalue les impacts tarifaires.Veuillez contacter votre vendeur pour obtenir de l’aide.
Livraison gratuite aux États-Unis continentaux à partir de 50 $ US. Des conditions s'appliquent
Référence fabricant
74HCT573PW,118
74HCT Series 5.5 V 3-State Octal D-Type Transparent Latch - TSSOP-20
| | |||||||||||
| | |||||||||||
| Nom du fabricant: | Nexperia | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :2500 par Reel Style d'emballage :TSSOP-20 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
Nexperia 74HCT573PW,118 - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Statut du produit:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=74HCT573PW,118&field4=Nexperia&field18=https://p1na.futureelectronics.com/fr/p/semiconductors--logic--74-series--a-hc-t/74hct573pw-118-nexperia-8004912
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=74HCT573PW,118&field4=Nexperia&field18=https://p1na.futureelectronics.com/fr/p/semiconductors--logic--74-series--a-hc-t/74hct573pw-118-nexperia-8004912
Nexperia 74HCT573PW,118 - Caractéristiques techniques
| Logic Circuit: | Latch |
| Family: | A/HC/T/U |
| No of Functions / Channels: | 8 |
| Output Characteristics: | 3-ST |
| Supply Voltage-Nom: | 5V |
| Supply Current: | 8µA |
| Power Dissipation: | 500mW |
| Propagation Delay: | 35ns |
| Operating Temperature: | -40°C to +125°C |
| Capacitance: | 3.5pF |
| No of Inputs: | 8 |
| No of Outputs: | Eight |
| High Level Output Current: | -7.8mA |
| Low Level Output Current: | 7.8mA |
| No of Pins: | 20 |
| Moisture Sensitivity Level: | 1 |
| Style d'emballage : | TSSOP-20 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The 74HCT573PW is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable (LE) input and an output enable OEinput are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.
Features:
- Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
- Useful as input or output port for microprocessors and microcomputers
- 3-state non-inverting outputs for bus oriented applications
- Common 3-state output enable input
- Functionally identical to 74HC563; 74HCT563 and 74HC373; 74HCT373
- Complies with JEDEC standard no. 7A
- ESD protection:
- HBM EIA/JESD22-A114-C exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Specified from -40 Cel to +85 Cel from -40 Cel +125 Cel
View the complete family of 74HCT573 Latch
Emballages disponibles
Qté d'emballage(s) :
2500 par Reel
Style d'emballage :
TSSOP-20
Méthode de montage :
Surface Mount