Référence fabricant
SY100S834LZG
SY100S834 Series 3.3 V Dual Differential LVPECL to LVTTL Translator - SOIC-16
| | |||||||||||
| | |||||||||||
| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :48 par Tube Style d'emballage :SOIC-16 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
Microchip SY100S834LZG - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
**Update to previous FPCN 98050******Revise affected parts list to remove SY89829UHY, SY89829UHY-TR and SY55856UHG catalog part number since these parts were EOL?ed****Description of Change:Qualification of UNIG as a new final test site for various products available in Tube and Tape & Reel packing media.Reason for Change:To improve manufacturability and on-time delivery performance by qualifying UNIG as a new final test site.
Description of Change:Implement top marking changes for SY100S834LZG and SY100S834LZG-TR catalog part numbers (CPN) in 16L SOIC (.150in)Pre and Post Change Summary: See attachedImpacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing top marking changes.Change Implementation Status:In ProgressEstimated First Ship Date:January 15, 2024 (date code: 2403)Note: Please be advised that after the estimated first ship date customers may receive pre and post change parts.Time Table Summary: See attached
Statut du produit:
Microchip SY100S834LZG - Caractéristiques techniques
| No of Channels: | 6 |
| Input Type: | LVPECL |
| Output Type: | LVTTL |
| Supply Voltage: | 3V to 3.8V |
| Style d'emballage : | SOIC-16 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The SY100S834LZG is a low Skew Clock generation chip designed explicity for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned
These devices can be driven by either a differential or single-ended ECL or, if postive power supplies are used, PECL input signal. in addition by using the VBB output should be connected to the CLK input and bypassed to ground via 0.01 µ F capacitor
Features:
- Power supply options
- 3.3 V (SY100S834L)
- 5 V (SY100S834)
- 50ps output-to-output skew
- Synchronous enable/disable
- Master reset for Synchronization
- Internal 75 KO input pulldown resistors
- Available in 16-pin SOIC package
Applications:
- Industrail
- Automotive
View the complete Differential Translator
Emballages disponibles
Qté d'emballage(s) :
48 par Tube
Style d'emballage :
SOIC-16
Méthode de montage :
Surface Mount