onsemi | MC100EP196FAG

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.

The delay section consists of a programmable matrix of gates and multiplexers. The delay increment of the EP196 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0].

The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.

Key Features:

• Maximum Frequency > 1.2 GHz Typical
• Programmable Range: 0 ns to 10 ns
• Delay Range: 2.4 ns to 12.4 ns
• 10 ps Increments
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the EN Pin Will Force Q to Logic Low
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
• VBB Output Reference Voltage
• Pb−Free Packages are Available