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Manufacturer Part #
APA450-PQG208
APA Series 450000 System Gates 158 I/O 108 kb ProASICPLUS® FPGA - PQFP-208
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:24 per Tray Package Style:PQFP-208 Mounting Method:Surface Mount | ||||||||||
| Date Code: | 2403 | ||||||||||
Microchip APA450-PQG208 - Product Specification
Shipping Information:
ECCN:
PCN Information:
EOL Description:The selected A54SX16A, A54SX32A, A54SX72A, APA075, APA1000, APA150, APA300, APA450, APA600 and APA750 device families will be moving to End of Life (EOL) status effective today. These selected device families will no longer be offered after December 1, 2026.Reason for EOL:No longer have manufacturing support for the CPN listed in the attachment.Last date for bookings (LTB): December 1, 2025Last date for shipments (LTS): December 1, 2026
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
Microchip APA450-PQG208 - Technical Attributes
| System Gates: | 450000 |
| No of I/O Lines: | 158 |
| Operating Frequency-Max: | 180MHz |
| RAM Size (Bits): | 108kb |
| Supply Voltage: | 2.3V to 2.7V |
| Operating Temp Range: | 0°C to 70°C |
| Storage Temperature Range: | -55°C to +110°C |
| Interface Type: | Jtag |
| Temperature Grade: | Commercial |
| Moisture Sensitivity Level: | 3 |
| Package Style: | PQFP-208 |
| Mounting Method: | Surface Mount |
Available Packaging
Package Qty:
24 per Tray
Package Style:
PQFP-208
Mounting Method:
Surface Mount