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Manufacturer Part #
M2S090TS-1FG484I
FPGA - Field Programmable Gate Array, FPBGA-484, SmartFusion2 SoC
Microchip M2S090TS-1FG484I - Product Specification
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PCN Information:
*** Update for FPCN 110718 ***Description of Change:Qualification of MTAI as an additional In-House Programming (IHP) site for selected M2GL005x, M2GL010xx, M2GL025xx, M2GL050xx, M2GL060xx, M2GL090xx, M2GL150xx, M2S005x, M2S010xx, M2S025xx, M2S050xx, M2S060xx, M2S090xx and M2S150xx device families available in various packages.Reason for Change:To improve manufacturability by qualifying MTAI as an additional in-house programming site.Estimated First Ship Date:February 14, 2025 (date code: 2507)Revision History:January 14, 2025: Issued final notification.February 06, 2025: Re-issued final notification to remove M2S010-1VFG256I, M2GL005-VFG256I, M2S005-VFG256IZ049, M2GL005-VFG256, M2S005S-DIELOTWX551, M2S005S DIELOTWX552, M2S005S-DIELOTW, M2S025TS-DIELOTW, M2S025TS-DIELOTWX553, M2S010TS-DIELOTW, M2S150TS-DIELOTWX555, M2S150TS-DIELOTW, M2S150TS DIELOTWX556, M2S090TS-DIELOTW, M2S060TS-DIELOTWX554, M2S060TS-DIELOTW, M2S025-FCSG325, M2S025T-FCSG158IZ222, M2S025T-1FCSG158HZ221 and M2GL025T FGG484 catalog part numbers (CPN) and added M2S010-1TQG144Q384, M2S010-1TQG144Q383, M2S025TS-VFG256S0055, M2S025TS-FGG484H0414, M2S060TS FGG484IH0437 and M2S060TS-FGG484IH0447 catalog part numbers (CPN). April 07, 2025: Re-issued final notification to remove CPNs M2GL025-1FGG484T1X7, M2GL005S-1VFG256T2, M2GL010-1FGG484T1 and M2GL025-1FGG484T1 in the Affected CPN due to updated scope. Remove CPNs M2S090-FCS325X339, M2GL010-FG484MX399 and M2S090-FGG676ORT due to being EOL.
Description of Change:Qualification of MTAI as an additional In-House Programming (IHP) site for selected M2GL005x, M2GL010xx, M2GL025xx, M2GL050xx, M2GL060xx, M2GL090xx, M2GL150xx, M2S005x, M2S010xx, M2S025xx, M2S050xx, M2S060xx, M2S090xx and M2S150xx device families available in various packages.Reason for Change:To improve manufacturability by qualifying MTAI as an additional in-house programming site.Estimated First Ship Date:February 14, 2025 (date code: 2507)Revision History:January 14, 2025: Issued final notification.February 06, 2025: Re-issued final notification to remove M2S010-1VFG256I, M2GL005-VFG256I, M2S005-VFG256IZ049, M2GL005-VFG256, M2S005S-DIELOTWX551, M2S005S-DIELOTWX552, M2S005S-DIELOTW, M2S025TS-DIELOTW, M2S025TS-DIELOTWX553, M2S010TS-DIELOTW, M2S150TS-DIELOTWX555, M2S150TS-DIELOTW, M2S150TS-DIELOTWX556, M2S090TS-DIELOTW, M2S060TS-DIELOTWX554, M2S060TS-DIELOTW, M2S025-FCSG325, M2S025T-FCSG158IZ222, M2S025T-1FCSG158HZ221 and M2GL025T-FGG484 catalog partnumbers (CPN) and added M2S0101TQG144Q384, M2S010-1TQG144Q383, M2S025TS-VFG256S0055, M2S025TS-FGG484H0414, M2S060TS-FGG484IH0437 and M2S060TS-FGG484IH0447 catalog part numbers (CPN).
Description of Change:In the revision E of this document, the Table 3-2 was updated inserting a note to assert that the product is designed and validated for operation within the junction temperature (TJ) range.Reason for Change: To Improve ProductivityDate Document Changes Effective: 28 Jan 2025Revision History:January 29, 2025: Issued Document PCN.January 31, 2025: Re-issued Document PCN to revise affected CPN list.
Description of Change:Qualification of MTAI as an additional In-House Programming (IHP) site for selected M2GL005x, M2GL010xx, M2GL025xx, M2GL050xx, M2GL060xx, M2GL090xx, M2GL150xx, M2S005x, M2S010xx, M2S025xx, M2S050xx, M2S060xx, M2S090xx and M2S150xx device families available in various packages.Reason for Change:To improve manufacturability by qualifying MTAI as an additional in-house programming site.
Microchip has released a new Datasheet for the SmartFusion 2 and IGLOO 2 Automotive Grade 2 Datasheet of devices. If you are using one of these devices please read the document located at SmartFusion 2 and IGLOO 2 Automotive Grade 2 Datasheet.Notification Status: FinalDescription of Change:Revision B The following is a list changes made in this revision:? Added the Ordering Information section for Automotive Grade 2 IGLOO 2 and SmartFusion 2 SoC.? Updated the hyperlink for the IGLOO? 2 FPGA Product Brief in the Product Briefs and Pin Descriptions section.? Updated the table links in Section 1.1 Operating Conditions.? Removed Bank0 and Bank5 for VREFx from Table 1-2.? Added Note 3 on MSIO, MSIOD, and DEVRST pins to Table 5-3.? Updated Table 7-27 by adding a note to the table on JTAG IOs.? Updated Table 7-28, Table 7-29, Table 7-31, and Table 7-32 by adding note that the power-up to Functional time in the tables do not consider SUSPEND_MODE.Impacts to Data Sheet: NoneReason for Change: To Improve Productivity.Change Implementation Status: CompleteDate Document Changes Effective: 24 Jun 2024NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Microchip has released a new Document for the SmartFusion 2 and IGLOO 2 FPGA High-Speed Serial Interface User Guide of devices.Description of Change:The following is a summary of the changes made in this revision.? Added a note in 4.6.2.1.5. AXI3 Slave Block regarding the supported read and write burst types.? Added third point in the note under Table 4-4 to describe the usage of Byte 7 of the TLP Header when word widths less than 64-bit are required.? Added ?PCIE_? prefix to the PCIE_DEV2SCR and PCIE_LINK2SCR registers in 4.10.10. PCIe Control and Status Registers.? Updated Figure 6-12. Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: Complete
Microchip has released a new Datasheet for the IGLOO? 2 FPGA and SmartFusion? 2 SoC FPGA Datasheet of devices. If you are using one of these devices please read the document located at IGLOO? 2 FPGA and SmartFusion? 2 SoC FPGA Datasheet.Notification Status: FinalDescription of Change: ? The "INTRODUCTION" section was updated by adding part numbers with prefixes for IGLOO 2 and SmartFusion 2.? Updated the minimum timing values of SP6-SP9 in Table 3-274.? Added ?DEVRST_N pulse width? details to DEVRST_N Characteristics in Table 3-278.? Removed bank numbers for FDDR and MDDR Reference voltage supply in Table 3-2.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 31 January 2024NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices::N/A
Description of Change: Updated Errata Number 1.20 in Table 1 to indicate that an errata is available for the M2S060 device. ? Updated 1.20. SRAM-PUF System Services May Take Two to Three Seconds to Complete section to indicate the errata has been fixed in devices manufactured after December 2016, resulting in faster (100 ms) running of SRAM-PUF system services. ? Replaced the Microsemi links with the Microchip links throughout the document.Reason for Change: To Improve Productivity
Microchip has released a new Errata for the SmartFusion 2 and IGLOO 2 FPGA High-Speed Serial Interface User Guide of devices.Description of Change: The following is a summary of the changes made in this revision:? Added a line in the Introduction section regarding part numbers starting with M2S and M2GL.? Added PCIe backend FPGA bandwidth requirements or PCIe traffic limitation requirements. See 4.9.5. User Data Throughput. For moreinformation, see PCN: SmartFusion 2, IGLOO 2, and RTG4 FPGA PCIe Receive FIFO Full(https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/can/SF2_IGL2_RTG4_PCIe_Receive_FIFO_Full_CN.pdf).? Updated PCIE_CREDIT_ALLOCATION_0 and PCIE_CREDIT_ALLOCATION_1 registers from RO to R/W. See Table 4-15.? Updated the bit field definition of CREDIT_ALLOCATION1_27_16 and CREDIT_ALLOCATION1_7_0 registers. See Table 4-53 and Table 4-54.Reason for Change: To Improve Productivity
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Available Packaging
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60 per Tray