Manufacturer Part #
MPF Series 512 I/O Lines SMT PolarFire™ Non-Volatile FPGA - Flip Chip 484
Description of Change:Release of revised timing data in Libero SoC v2021.2 for selected products in the PolarFire FPGA device family, including selected CPSOM-MPFxxx, MPF100Txxx, MPF200Txxx, MPF300Txxx and MPF500Txxx device families.Reason for Change:Release updated PolarFire FPGA timing data along with Libero SoC v2021.2 to improve the accuracy of Static Timing Analysis (STA) performed on PolarFire designs, as described in the attached Customer Notice.
Description of Change:Implement Microchip Part Aging Policy, Recertification and Combination rules, Labels and Packing Changes for selected Microsemi Field Programmable Gate Array (FPGA) and Mixed Signal and ASIC(MSA) products.Pre Change: Using Microsemi’s packing processPost Change:Using Microchip’s packing processPre and Post Change Summary:NOTE: See attached Packing Pre and Post Changes for the changes Impacts to Data Sheet:NoneChange Impact:NoneReason for Change:To improve productivity by standardizing the packing method as part of the integration of Microsemi and Microchip.Change Implementation Status:In ProgressEstimated Implementation Date: February 15, 2021 (date code: 2108)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and business conditions.Time Table Summary: see attachedRevision History:January 18, 2021: Issued final notification. Provided estimated first ship date to be on February 15, 2021.The change described in this PCN does not alter Microchip’s current regulatory compliance regarding the material content of the applicable products.
Description of Change: Implement Microchip Top marking changes for selected Microsemi Field-Programmable Gate Arrays (FPGAs) products available in various packages.Pre Change: Microsemi top marking format and traceability codePost Change: Microchip top marking format and traceability codePre and Post Change Summary: see attachedImpacts to Data Sheet: Where applicableChange Impact: NoneReason for Change:To improve manufacturability and traceability by standardizing marking format for selected Microsemi products as part of the integration of Microchip and Microsemi.Change Implementation Status: In ProgressEarliest Implementation Date: March 1, 2021 (Date code: 2110)Note: The earliest implementation date is the earliest date that we may implement any combination of the changes listed in this PCN as we will not implement any of the proposed changes prior to this date. After the earliest implementation date these changes may occur to any product over the course of many months depending on inventory levels and businessconditions.Time Table Summary:
PolarFire FPGA VICM Clarification for HSIODescription:This is a PolarFire Datasheet documentation change to the note for table 16 which relaxes the HSIO differential receiver maximum input common mode from a maximum VICM value of VDDI � 0.4 V to a new maximum VICM value of VDDI 0.24 V.Reason for ChangeThis change is to correct the PolarFire Datasheet table 16 notes that were too restrictive for HSIO differential receiver input common modes maximum ranges.
Maximum Read Frequency on Certain LSRAM Read Modes Has Been Reduced.DescriptionThe following LSRAM configurations have derated FMAX specifications.Reason for ChangeOn-going QA testing and verification exposed a timing criticality in a critical path within the LSRAM.Application ImpactUsers should upgrade to Libero 12.6 and re-run static timing using SmartTime if they are using one of the above LSRAM configurations and the design is running faster than the new limits listed in the table above.Method of Identifying Changed ProductBy part number.
Ongoing Software Quality Testing on Libero SoC Has Found a Static Timing Analysis (STA) Coverage Issue for Specific Scenarios for SmartFusion2, IGLOO2, RTG4, and PolarFire Product Families.Description:With Libero SoC v12.5, Libero SoC v12.5 SP1, and Libero SoC v11.9 SP6, netlist tie-off information is now correctly being passed to SmartTime for a complete static timing analysis.Reason for Change:Post-Layout timing database information for combinational cells inputs with constant tie-offs ("1" or "0") was incorrectly passed to SmartTime, preventing complete analysis of the path through the combinational cell.
Description:A change has been implemented to the PolarFire two-port large SRAM configurator and dual-port large SRAM configurator. The LSRAM configurator engine for the Write Byte Enable selection divides the entire width of the memory into equal fragments controlled by each Write Byte Enable bit.Reason for Change:The PolarFire LSRAM configurator engine in Libero SoC v12.4 and prior releases could generate unequal fragments for each Write Byte Enable selection bit. Typically, the total width of the memory would have been divided into fragments of 10 bits and the most significant fragment would be the remainder bits. For example, a two-port large SRAM memory with write width of 16 and the Write Byte Enable selection would be divided into 10-bit and 6-bit fragments.The change is applied to the following:-PolarFire two-port large SRAM configurator-PolarFire dual-port large SRAM configurator
DescriptionA change has been implemented to the PolarFire two-port large SRAM configurator, dual-port large SRAM configurator, and CoreFIFO. The LSRAM configurator engine correctly generates asymmetric width configurations and optimizes the area for high-speed and low-power selections.Reason for Change:The PolarFire LSRAM configurator engine in Libero SoC v12.4 could generate incorrect and sub-optimal configurations of asymmetric widths for certain multiples of 64 or 72. Asymmetric width configurations occur when the width of the two ports of LSRAM are not equal (for example, a FIFO, where the width of the write port is 36 and the width of the read port is 72).The change is applied to the following:-PolarFire two-port large SRAM configurator-PolarFire dual-port large SRAM configurator-CoreFIFO
PolarFire PF_SPI and UJTAG Timing Change.Description:The timing model of most output signals from the UJTAG to the fabric were updated to be triggered on the falling edge of the clock rather than the rising edge.-The reset signal, fab_uj_trstb, going into the fabric is now considered asynchronous.-External timing checks are not included in the model. PF_SPI:-The timing model has been updated to allow proper timing checks through PF_SPI for CLK, SS, DI, DO signals.Reason for Change:The change has been made to reflect the actual implementation on silicon.