NXP | PCA9517AD,118

It is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.

Features:

• 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device
• Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
• Footprint and functional replacement for PCA9515/15A
• I2C-bus and SMBus compatible
• Active HIGH repeater enable input
• Open-drain input/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
• Powered-off high-impedance I2C-bus pins
• Port A operating supply voltage range of 0.9 V to 5.5 V
• Port B operating supply voltage range of 2.7 V to 5.5 V
• 5 V tolerant I2C-bus and enable pins
• 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
• less than 400 kHz because of the delays added by the repeater)
• ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SO8, TSSOP8 and HWSON8