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Référence fabricant
9DBL0452CKILF
Clock Buffer 9DBL0452C 4 O/P 3.3V PCIE BUF, ZO=85, TR
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| Nom du fabricant: | Renesas | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :490 par Tray | ||||||||||
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Renesas 9DBL0452CKILF - Spécifications du produit
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Subject: Register value update on 9DBL0xxxC, 9FGL0xxxD and 9SQL495xD product family.Description of Change: This notice is to inform you that Renesas is making the programming update as register byte-7 and byte-10 value on 9DBL0xxxC device, and register byte-10 value on 9FGL0xxxD and 9SQL495xD devices did not match datasheet descriptions. Renesas update on default register below. 1. 9DBL0xxxC: Updated register byte-7 value from 0x01 to 0x08 and updated register byte-10 value from 0xC0 to 0x40. Byte7 is a byte count register which is a scratch register. Byte-10 is an enables bit to allow user to access internal PLL M/N dividers. This change is to disable access to the internal PLL M/N dividers. No change to other register values. No change to part performance.2. 9FGL0xxxD: Updated register byte-10 value from 0xC0 to 0x40. Byte-10 is an enables bit to allow user to access internal PLL M/N dividers. This change is to disable access to the internal PLL M/N dividers. No change to other register values. No change to part performance 3. 9SQL495xD: Updated register byte-10 value from 0xC0 to 0x40. Byte-10 is an enables bit to allow user to access internal PLL M/N dividers. This change is to disable access to the internal PLL M/N dividers. No change to other register values. No change to part performanceReason for Change: To match the register value in datasheet description.
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Emballages disponibles
Qté d'emballage(s) :
490 par Tray