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Référence fabricant
74LVC573APW,118
74LVC Series 3.6 V SMT 3-State Octal D-type Transparent Latch - TSSOP-20
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| Nom du fabricant: | Nexperia | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :2500 par Reel Style d'emballage :TSSOP-20 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | 2426 | ||||||||||
Nexperia 74LVC573APW,118 - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Statut du produit:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=74LVC573APW,118&field4=Nexperia&field18=https://p1na.futureelectronics.com/fr/p/semiconductors--logic--74-series--a-lvc/74lvc573apw-118-nexperia-8092538
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=74LVC573APW,118&field4=Nexperia&field18=https://p1na.futureelectronics.com/fr/p/semiconductors--logic--74-series--a-lvc/74lvc573apw-118-nexperia-8092538
Nexperia 74LVC573APW,118 - Caractéristiques techniques
| Logic Circuit: | D-Type Latch |
| Family: | A/LVC/E/H/U |
| No of Functions / Channels: | 8 |
| Output Characteristics: | 3-ST |
| Supply Voltage-Nom: | 3.6V |
| Supply Current: | 100mA |
| Power Dissipation: | 500mW |
| Propagation Delay: | 18.8ns |
| Operating Temperature: | -40°C to +125°C |
| No of Inputs: | 10 |
| No of Outputs: | Eight |
| High Level Output Current: | -24mA |
| Low Level Output Current: | 24mA |
| No of Pins: | 20 |
| Moisture Sensitivity Level: | 1 |
| Style d'emballage : | TSSOP-20 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The 74LVC573APW is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 or 5 V environment.
Features:
- 5 V tolerant inputs/outputs, for interfacing with 5 V logic
- Supply voltage range from 1.2 to 3.6 V
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- High impedance when VCC =0 V
- Flow-through pin-out architecture
- Complies with JEDEC standard no. 8-1A
- ESD protection:
- HBM EIA/JESD22-A114-A exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Specified from -40 to +85 Cel and -40 to +125 Cel
View the 74LVC573 family of D-Type Transparent Latch
Emballages disponibles
Qté d'emballage(s) :
2500 par Reel
Style d'emballage :
TSSOP-20
Méthode de montage :
Surface Mount