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Référence fabricant
A3P125-PQG208I
FPGA ProASIC3 Family 1M Gates 231MHz 130nm (CMOS) Technology 1.5V 208-Pin PQFP
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :24 par Tray | ||||||||||
| Code de date: | |||||||||||
Microchip A3P125-PQG208I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
EOL Description:The selected End of Life (EOL) of selected A3P1000, A3P125, A3P250, A3P400, A3P600, A3P600L, A3PE3000, A3PE3000L, A3PE600, M1A3P1000, M1A3P250, M1A3P400, M1A3P600, M7A3P1000, M1A3PE300 and M1A3PE3000L device families will be moving to End of Life (EOL) status effective today. These selected device families will no longer be offered after December 1, 2026. Please review the attached parts affected listNote 1:Aligning with our commitment to product longevity, Microchip is currently qualifying a new assembly site as a potential alternative manufacturing source for the affected products. If the qualification is successfully completed, we intend to cancel the EOL notice and resume standard supply through the newly qualified site. We strongly encourage you to place your LTB orders as soon as possible to ensure uninterrupted supply and to mitigate any potential supply gaps during the qualification period. Please note that all LTB orders will be processed as NCNR. If the new assembly site is successfully qualified, a PCN will be issued to inform you of the change to assembly location and the EOL notice will be cancelled, which will also prompt a cancellation notice. At that time, clients will have the option to extend deliveries of their LTB orders beyond the LTS date. Reason for EOL:No longer have manufacturing support for the CPN listed in the attachment.Estimated Effective Dates:Customers affected by this EOL notice are advised to place last time buy (LTB) orders as follows:Last date for bookings (LTB): December 1, 2025Last date for shipments (LTS): December 1, 2026
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Microchip has released a new Datasheet for the ProASIC?3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. ? Corrected misaligned images?Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. ? Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
24 par Tray