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Référence fabricant

LPC1752FBD80,551

LPC17xx Series 64 kB Flash 16 kB RAM SMT 32-Bit-Microcontroller - LQFP-80

LPC1752FBD80,551 Fiche technique LPC1752FBD80,551 Documentation User Manual Selection Guide Leaflet LPC Discovery
Modèle ECAD: Convertissez ce fichier pour votre outil ECAD en téléchargeant gratuitement. En savoir plus sur le modèle ECAD.
Nom du fabricant:	NXP
Emballage standard:	Product Variant Information section Emballages disponibles Tray TraySelected Variant Qté: 1+ / Prix unitaire: $5.44 / Stock: 0 Qté: 1+$5.44 Stock: 0 Qté d'emballage(s) : 119 par Tray Style d'emballage : LQFP-80 Méthode de montage : Surface Mount
Code de date:

NXP LPC1752FBD80,551 - Caractéristiques techniques

Family Name:	LPC17xx
Core Processor:	ARM Cortex M3
Program Memory Type:	Flash
Flash Size (Bytes):	64kB
RAM Size:	16kB
Speed:	100MHz
No of I/O Lines:	52
InterfaceType / Connectivity:	CAN/I2C/SPI/UART/USB
Peripherals:	CAN/I2C/On-Chip-ADC/PWM/SPI/UART/USB/Watchdog
Number Of Timers:	4
Supply Voltage:	2.4V to 3.6V
Operating Temperature:	-40°C to +85°C
On-Chip ADC:	6-chx12-bit
Watchdog Timers:	1
Style d'emballage :	LQFP-80
Méthode de montage :	Surface Mount

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Fonctionnalités et applications

The LPC1758/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1758/56/54/52/51 operate at CPU frequencies of up to 100 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features :

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 100 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
On-chip SRAM includes:
Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
Serial interfaces
Other peripherals
Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Single 3.3 V power supply (2.4 V to 3.6 V).
One external interrupt input configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt (LPC1758 only), CAN bus activity, PORT0/2 pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
USB PLL for added flexibility.